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Re: [PATCH v1 2/2] riscv: opentitan: Connect opentitan SPI Host
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v1 2/2] riscv: opentitan: Connect opentitan SPI Host |
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Date: |
Wed, 23 Feb 2022 14:13:30 +1000 |
On Wed, Feb 23, 2022 at 7:45 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Wilfred Mallawa <wilfred.mallawa@wdc.com>
>
> Conenct spi host[1/0] to opentitan.
>
> Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
> ---
> hw/riscv/opentitan.c | 42 ++++++++++++++++++++++++++++++++----
> include/hw/riscv/opentitan.h | 16 ++++++++++++--
> 2 files changed, 52 insertions(+), 6 deletions(-)
>
> diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c
> index aec7cfa33f..abbe08d4d4 100644
> --- a/hw/riscv/opentitan.c
> +++ b/hw/riscv/opentitan.c
> @@ -1,7 +1,7 @@
> /*
> * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
> *
> - * Copyright (c) 2020 Western Digital
> + * Copyright (c) 2022 Western Digital
You don't need to update this
> *
> * Provides a board compatible with the OpenTitan FPGA platform:
> *
> @@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] = {
> [IBEX_DEV_FLASH] = { 0x20000000, 0x80000 },
> [IBEX_DEV_UART] = { 0x40000000, 0x1000 },
> [IBEX_DEV_GPIO] = { 0x40040000, 0x1000 },
> - [IBEX_DEV_SPI] = { 0x40050000, 0x1000 },
> + [IBEX_DEV_SPI_DEVICE] = { 0x40050000, 0x1000 },
This will conflict with the latest RISC-V tree as:
"hw: riscv: opentitan: fixup SPI addresses" has been applied.
Alistair
> [IBEX_DEV_I2C] = { 0x40080000, 0x1000 },
> [IBEX_DEV_PATTGEN] = { 0x400e0000, 0x1000 },
> [IBEX_DEV_TIMER] = { 0x40100000, 0x1000 },
> [IBEX_DEV_SENSOR_CTRL] = { 0x40110000, 0x1000 },
> [IBEX_DEV_OTP_CTRL] = { 0x40130000, 0x4000 },
> [IBEX_DEV_USBDEV] = { 0x40150000, 0x1000 },
> + [IBEX_DEV_SPI_HOST0] = { 0x40300000, 0x1000 },
> + [IBEX_DEV_SPI_HOST1] = { 0x40310000, 0x1000 },
> [IBEX_DEV_PWRMGR] = { 0x40400000, 0x1000 },
> [IBEX_DEV_RSTMGR] = { 0x40410000, 0x1000 },
> [IBEX_DEV_CLKMGR] = { 0x40420000, 0x1000 },
> @@ -118,11 +120,18 @@ static void lowrisc_ibex_soc_init(Object *obj)
> object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART);
>
> object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER);
> +
> + for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) {
> + object_initialize_child(obj, "spi_host[*]", &s->spi_host[i],
> + TYPE_IBEX_SPI_HOST);
> + }
> }
>
> static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
> {
> const MemMapEntry *memmap = ibex_memmap;
> + DeviceState *dev;
> + SysBusDevice *busdev;
> MachineState *ms = MACHINE(qdev_get_machine());
> LowRISCIbexSoCState *s = RISCV_IBEX_SOC(dev_soc);
> MemoryRegion *sys_mem = get_system_memory();
> @@ -207,10 +216,35 @@ static void lowrisc_ibex_soc_realize(DeviceState
> *dev_soc, Error **errp)
> qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)),
> IRQ_M_TIMER));
>
> + /* SPI-Hosts */
> + for (int i = 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) {
> + dev = DEVICE(&(s->spi_host[i]));
> + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) {
> + return;
> + }
> + busdev = SYS_BUS_DEVICE(dev);
> + sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base);
> +
> + switch (i) {
> + case OPENTITAN_SPI_HOST0:
> + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_SPI_HOST0_ERR_IRQ));
> + sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_SPI_HOST0_SPI_EVENT_IRQ));
> + break;
> + case OPENTITAN_SPI_HOST1:
> + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_SPI_HOST1_ERR_IRQ));
> + sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic),
> + IBEX_SPI_HOST1_SPI_EVENT_IRQ));
> + break;
> + }
> + }
> +
> create_unimplemented_device("riscv.lowrisc.ibex.gpio",
> memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
> - create_unimplemented_device("riscv.lowrisc.ibex.spi",
> - memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
> + create_unimplemented_device("riscv.lowrisc.ibex.spi_device",
> + memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size);
> create_unimplemented_device("riscv.lowrisc.ibex.i2c",
> memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size);
> create_unimplemented_device("riscv.lowrisc.ibex.pattgen",
> diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h
> index eac35ef590..3a3f412ef8 100644
> --- a/include/hw/riscv/opentitan.h
> +++ b/include/hw/riscv/opentitan.h
> @@ -1,7 +1,7 @@
> /*
> * QEMU RISC-V Board Compatible with OpenTitan FPGA platform
> *
> - * Copyright (c) 2020 Western Digital
> + * Copyright (c) 2022 Western Digital
> *
> * This program is free software; you can redistribute it and/or modify it
> * under the terms and conditions of the GNU General Public License,
> @@ -23,11 +23,16 @@
> #include "hw/intc/sifive_plic.h"
> #include "hw/char/ibex_uart.h"
> #include "hw/timer/ibex_timer.h"
> +#include "hw/ssi/ibex_spi_host.h"
> #include "qom/object.h"
>
> #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
> OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
>
> +#define OPENTITAN_NUM_SPI_HOSTS 2
> +#define OPENTITAN_SPI_HOST0 0
> +#define OPENTITAN_SPI_HOST1 1
> +
> struct LowRISCIbexSoCState {
> /*< private >*/
> SysBusDevice parent_obj;
> @@ -37,6 +42,7 @@ struct LowRISCIbexSoCState {
> SiFivePLICState plic;
> IbexUartState uart;
> IbexTimerState timer;
> + IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS];
>
> MemoryRegion flash_mem;
> MemoryRegion rom;
> @@ -57,8 +63,10 @@ enum {
> IBEX_DEV_FLASH,
> IBEX_DEV_FLASH_VIRTUAL,
> IBEX_DEV_UART,
> + IBEX_DEV_SPI_DEVICE,
> + IBEX_DEV_SPI_HOST0,
> + IBEX_DEV_SPI_HOST1,
> IBEX_DEV_GPIO,
> - IBEX_DEV_SPI,
> IBEX_DEV_I2C,
> IBEX_DEV_PATTGEN,
> IBEX_DEV_TIMER,
> @@ -88,6 +96,10 @@ enum {
>
> enum {
> IBEX_TIMER_TIMEREXPIRED0_0 = 126,
> + IBEX_SPI_HOST1_SPI_EVENT_IRQ = 153,
> + IBEX_SPI_HOST1_ERR_IRQ = 152,
> + IBEX_SPI_HOST0_SPI_EVENT_IRQ = 151,
> + IBEX_SPI_HOST0_ERR_IRQ = 150,
> IBEX_UART0_RX_PARITY_ERR_IRQ = 8,
> IBEX_UART0_RX_TIMEOUT_IRQ = 7,
> IBEX_UART0_RX_BREAK_ERR_IRQ = 6,
> --
> 2.35.1
>