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[PATCH v2 07/12] mos6522: add register names to register read/write trac
From: |
Mark Cave-Ayland |
Subject: |
[PATCH v2 07/12] mos6522: add register names to register read/write trace events |
Date: |
Thu, 24 Feb 2022 11:59:51 +0000 |
This helps to follow how the guest is programming the mos6522 when debugging.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/misc/mos6522.c | 10 ++++++++--
hw/misc/trace-events | 4 ++--
2 files changed, 10 insertions(+), 4 deletions(-)
diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 093cc83dcf..aaae195d63 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -36,6 +36,12 @@
#include "qemu/module.h"
#include "trace.h"
+
+static const char *mos6522_reg_names[16] = {
+ "ORB", "ORA", "DDRB", "DDRA", "T1CL", "T1CH", "T1LL", "T1LH",
+ "T2CL", "T2CH", "SR", "ACR", "PCR", "IFR", "IER", "ANH"
+};
+
/* XXX: implement all timer modes */
static void mos6522_timer1_update(MOS6522State *s, MOS6522Timer *ti,
@@ -310,7 +316,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned
size)
}
if (addr != VIA_REG_IFR || val != 0) {
- trace_mos6522_read(addr, val);
+ trace_mos6522_read(addr, mos6522_reg_names[addr], val);
}
return val;
@@ -321,7 +327,7 @@ void mos6522_write(void *opaque, hwaddr addr, uint64_t val,
unsigned size)
MOS6522State *s = opaque;
MOS6522DeviceClass *mdc = MOS6522_GET_CLASS(s);
- trace_mos6522_write(addr, val);
+ trace_mos6522_write(addr, mos6522_reg_names[addr], val);
switch (addr) {
case VIA_REG_B:
diff --git a/hw/misc/trace-events b/hw/misc/trace-events
index 1c373dd0a4..c1ea57de31 100644
--- a/hw/misc/trace-events
+++ b/hw/misc/trace-events
@@ -95,8 +95,8 @@ imx7_gpr_write(uint64_t offset, uint64_t value) "addr 0x%08"
PRIx64 "value 0x%08
mos6522_set_counter(int index, unsigned int val) "T%d.counter=%d"
mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d
counter=0x%"PRId64 " delta_next=0x%"PRId64
mos6522_set_sr_int(void) "set sr_int"
-mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
-mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
+mos6522_write(uint64_t addr, const char *name, uint64_t val) "reg=0x%"PRIx64 "
[%s] val=0x%"PRIx64
+mos6522_read(uint64_t addr, const char *name, unsigned val) "reg=0x%"PRIx64 "
[%s] val=0x%x"
# npcm7xx_clk.c
npcm7xx_clk_read(uint64_t offset, uint32_t value) " offset: 0x%04" PRIx64 "
value: 0x%08" PRIx32
--
2.20.1
- [PATCH v2 01/12] mos6522: add defines for IFR bit flags, (continued)
- [PATCH v2 01/12] mos6522: add defines for IFR bit flags, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 02/12] mac_via: use IFR bit flag constants for VIA1 IRQs, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 06/12] mos6522: use device_class_set_parent_reset() to propagate reset to parent, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 05/12] mos6522: remove update_irq() and set_sr_int() methods from MOS6522DeviceClass, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 04/12] mos6522: switch over to use qdev gpios for IRQs, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 08/12] mos6522: add "info via" HMP command for debugging, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 09/12] mos6522: record last_irq_levels in mos6522_set_irq(), Mark Cave-Ayland, 2022/02/24
- [PATCH v2 03/12] mac_via: use IFR bit flag constants for VIA2 IRQs, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 07/12] mos6522: add register names to register read/write trace events,
Mark Cave-Ayland <=
- [PATCH v2 10/12] mac_via: make SCSI_DATA (DRQ) bit live rather than latched, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 11/12] mos6522: implement edge-triggering for CA1/2 and CB1/2 control line IRQs, Mark Cave-Ayland, 2022/02/24
- [PATCH v2 12/12] macio/pmu.c: remove redundant code, Mark Cave-Ayland, 2022/02/24