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[PATCH v5 48/49] target/ppc: implement plxssp/pstxssp
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From: |
matheus . ferst |
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Subject: |
[PATCH v5 48/49] target/ppc: implement plxssp/pstxssp |
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Date: |
Fri, 25 Feb 2022 18:09:35 -0300 |
From: Leandro Lupori <leandro.lupori@eldorado.org.br>
Implement instructions plxssp/pstxssp and port lxssp/stxssp to
decode tree.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Leandro Lupori <leandro.lupori@eldorado.org.br>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
---
target/ppc/insn32.decode | 2 +
target/ppc/insn64.decode | 6 ++
target/ppc/translate.c | 29 +++------
target/ppc/translate/vsx-impl.c.inc | 93 +++++++++++++++--------------
4 files changed, 62 insertions(+), 68 deletions(-)
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
index 37b6470503..1641a31894 100644
--- a/target/ppc/insn32.decode
+++ b/target/ppc/insn32.decode
@@ -604,6 +604,8 @@ VCLRRB 000100 ..... ..... ..... 00111001101 @VX
LXSD 111001 ..... ..... .............. 10 @DS
STXSD 111101 ..... ..... .............. 10 @DS
+LXSSP 111001 ..... ..... .............. 11 @DS
+STXSSP 111101 ..... ..... .............. 11 @DS
LXV 111101 ..... ..... ............ . 001 @DQ_TSX
STXV 111101 ..... ..... ............ . 101 @DQ_TSX
LXVP 000110 ..... ..... ............ 0000 @DQ_TSXP
diff --git a/target/ppc/insn64.decode b/target/ppc/insn64.decode
index b7426f5b24..691e8fe6c0 100644
--- a/target/ppc/insn64.decode
+++ b/target/ppc/insn64.decode
@@ -190,6 +190,12 @@ PLXSD 000001 00 0--.-- .................. \
PSTXSD 000001 00 0--.-- .................. \
101110 ..... ..... ................ @8LS_D
+PLXSSP 000001 00 0--.-- .................. \
+ 101011 ..... ..... ................ @8LS_D
+
+PSTXSSP 000001 00 0--.-- .................. \
+ 101111 ..... ..... ................ @8LS_D
+
PLXV 000001 00 0--.-- .................. \
11001 ...... ..... ................ @8LS_D_TSX
PSTXV 000001 00 0--.-- .................. \
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 1ef2eeeead..408ae26173 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6668,39 +6668,24 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d,
arg_PLS_D *a)
#include "translate/branch-impl.c.inc"
-/* Handles lfdp, lxssp */
+/* Handles lfdp */
static void gen_dform39(DisasContext *ctx)
{
- switch (ctx->opcode & 0x3) {
- case 0: /* lfdp */
+ if ((ctx->opcode & 0x3) == 0) {
if (ctx->insns_flags2 & PPC2_ISA205) {
return gen_lfdp(ctx);
}
- break;
- case 3: /* lxssp */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_lxssp(ctx);
- }
- break;
}
return gen_invalid(ctx);
}
-/* handles stfdp, lxv, stxssp lxvx */
+/* Handles stfdp */
static void gen_dform3D(DisasContext *ctx)
{
- if ((ctx->opcode & 3) != 1) { /* DS-FORM */
- switch (ctx->opcode & 0x3) {
- case 0: /* stfdp */
- if (ctx->insns_flags2 & PPC2_ISA205) {
- return gen_stfdp(ctx);
- }
- break;
- case 3: /* stxssp */
- if (ctx->insns_flags2 & PPC2_ISA300) {
- return gen_stxssp(ctx);
- }
- break;
+ if ((ctx->opcode & 3) == 0) { /* DS-FORM */
+ /* stfdp */
+ if (ctx->insns_flags2 & PPC2_ISA205) {
+ return gen_stfdp(ctx);
}
}
return gen_invalid(ctx);
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index a6e9417f2d..a980a79b78 100644
--- a/target/ppc/translate/vsx-impl.c.inc
+++ b/target/ppc/translate/vsx-impl.c.inc
@@ -288,29 +288,6 @@ VSX_VECTOR_LOAD_STORE_LENGTH(stxvl)
VSX_VECTOR_LOAD_STORE_LENGTH(stxvll)
#endif
-#define VSX_LOAD_SCALAR_DS(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 xth; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- xth = tcg_temp_new_i64(); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0x03); \
- gen_qemu_##operation(ctx, xth, EA); \
- set_cpu_vsr(rD(ctx->opcode) + 32, xth, true); \
- /* NOTE: cpu_vsrl is undefined */ \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
-}
-
-VSX_LOAD_SCALAR_DS(lxssp, ld32fs)
-
#define VSX_STORE_SCALAR(name, operation) \
static void gen_##name(DisasContext *ctx) \
{ \
@@ -460,29 +437,6 @@ static void gen_stxvb16x(DisasContext *ctx)
tcg_temp_free_i64(xsl);
}
-#define VSX_STORE_SCALAR_DS(name, operation) \
-static void gen_##name(DisasContext *ctx) \
-{ \
- TCGv EA; \
- TCGv_i64 xth; \
- \
- if (unlikely(!ctx->altivec_enabled)) { \
- gen_exception(ctx, POWERPC_EXCP_VPU); \
- return; \
- } \
- xth = tcg_temp_new_i64(); \
- get_cpu_vsr(xth, rD(ctx->opcode) + 32, true); \
- gen_set_access_type(ctx, ACCESS_INT); \
- EA = tcg_temp_new(); \
- gen_addr_imm_index(ctx, EA, 0x03); \
- gen_qemu_##operation(ctx, xth, EA); \
- /* NOTE: cpu_vsrl is undefined */ \
- tcg_temp_free(EA); \
- tcg_temp_free_i64(xth); \
-}
-
-VSX_STORE_SCALAR_DS(stxssp, st32fs)
-
static void gen_mfvsrwz(DisasContext *ctx)
{
if (xS(ctx->opcode) < 32) {
@@ -2345,8 +2299,53 @@ static bool do_plstxsd_PLS_D(DisasContext *ctx,
arg_PLS_D *a, bool store)
return do_lstxsd(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
}
+static bool do_lstxssp(DisasContext *ctx, int rt, int ra, TCGv displ, bool
store)
+{
+ TCGv ea;
+ TCGv_i64 xt;
+
+ REQUIRE_VECTOR(ctx);
+
+ xt = tcg_temp_new_i64();
+
+ gen_set_access_type(ctx, ACCESS_INT);
+ ea = do_ea_calc(ctx, ra, displ);
+
+ if (store) {
+ get_cpu_vsr(xt, rt + 32, true);
+ gen_qemu_st32fs(ctx, xt, ea);
+ } else {
+ gen_qemu_ld32fs(ctx, xt, ea);
+ set_cpu_vsr(rt + 32, xt, true);
+ set_cpu_vsr(rt + 32, tcg_constant_i64(0), false);
+ }
+
+ tcg_temp_free(ea);
+ tcg_temp_free_i64(xt);
+
+ return true;
+}
+
+static bool do_lstxssp_DS(DisasContext *ctx, arg_D *a, bool store)
+{
+ return do_lstxssp(ctx, a->rt, a->ra, tcg_constant_tl(a->si), store);
+}
+
+static bool do_plstxssp_PLS_D(DisasContext *ctx, arg_PLS_D *a, bool store)
+{
+ arg_D d;
+
+ if (!resolve_PLS_D(ctx, &d, a)) {
+ return true;
+ }
+
+ return do_lstxssp(ctx, d.rt, d.ra, tcg_constant_tl(d.si), store);
+}
+
TRANS_FLAGS2(ISA300, LXSD, do_lstxsd_DS, false)
TRANS_FLAGS2(ISA300, STXSD, do_lstxsd_DS, true)
+TRANS_FLAGS2(ISA300, LXSSP, do_lstxssp_DS, false)
+TRANS_FLAGS2(ISA300, STXSSP, do_lstxssp_DS, true)
TRANS_FLAGS2(ISA300, STXV, do_lstxv_D, true, false)
TRANS_FLAGS2(ISA300, LXV, do_lstxv_D, false, false)
TRANS_FLAGS2(ISA310, STXVP, do_lstxv_D, true, true)
@@ -2357,6 +2356,8 @@ TRANS_FLAGS2(ISA310, STXVPX, do_lstxv_X, true, true)
TRANS_FLAGS2(ISA310, LXVPX, do_lstxv_X, false, true)
TRANS64_FLAGS2(ISA310, PLXSD, do_plstxsd_PLS_D, false)
TRANS64_FLAGS2(ISA310, PSTXSD, do_plstxsd_PLS_D, true)
+TRANS64_FLAGS2(ISA310, PLXSSP, do_plstxssp_PLS_D, false)
+TRANS64_FLAGS2(ISA310, PSTXSSP, do_plstxssp_PLS_D, true)
TRANS64_FLAGS2(ISA310, PSTXV, do_lstxv_PLS_D, true, false)
TRANS64_FLAGS2(ISA310, PLXV, do_lstxv_PLS_D, false, false)
TRANS64_FLAGS2(ISA310, PSTXVP, do_lstxv_PLS_D, true, true)
--
2.25.1
- [PATCH v5 41/49] target/ppc: Implement xscmp{eq,ge,gt}qp, (continued)
- [PATCH v5 41/49] target/ppc: Implement xscmp{eq,ge,gt}qp, matheus . ferst, 2022/02/25
- [PATCH v5 42/49] target/ppc: Move xscmp{eq,ge,gt}dp to decodetree, matheus . ferst, 2022/02/25
- [PATCH v5 43/49] target/ppc: Move xs{max, min}[cj]dp to use do_helper_XX3, matheus . ferst, 2022/02/25
- [PATCH v5 44/49] target/ppc: Refactor VSX_MAX_MINC helper, matheus . ferst, 2022/02/25
- [PATCH v5 45/49] target/ppc: Implement xs{max,min}cqp, matheus . ferst, 2022/02/25
- [PATCH v5 46/49] target/ppc: Implement xvcvbf16spn and xvcvspbf16 instructions, matheus . ferst, 2022/02/25
- [PATCH v5 47/49] target/ppc: implement plxsd/pstxsd, matheus . ferst, 2022/02/25
- [PATCH v5 48/49] target/ppc: implement plxssp/pstxssp,
matheus . ferst <=
- [PATCH v5 49/49] target/ppc: implement lxvr[bhwd]/stxvr[bhwd]x, matheus . ferst, 2022/02/25