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[PULL v2 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim
From: |
Stafford Horne |
Subject: |
[PULL v2 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim |
Date: |
Sat, 26 Feb 2022 10:59:19 +0900 |
This will allow us to attach machine state attributes like
the device tree fdt.
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/openrisc/openrisc_sim.c | 30 ++++++++++++++++++++++++++++--
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 73fe383c2d..26d2370e60 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -37,6 +37,18 @@
#define KERNEL_LOAD_ADDR 0x100
+#define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim")
+#define OR1KSIM_MACHINE(obj) \
+ OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE)
+
+typedef struct Or1ksimState {
+ /*< private >*/
+ MachineState parent_obj;
+
+ /*< public >*/
+
+} Or1ksimState;
+
static struct openrisc_boot_info {
uint32_t bootstrap_pc;
} boot_info;
@@ -183,8 +195,10 @@ static void openrisc_sim_init(MachineState *machine)
openrisc_load_kernel(ram_size, kernel_filename);
}
-static void openrisc_sim_machine_init(MachineClass *mc)
+static void openrisc_sim_machine_init(ObjectClass *oc, void *data)
{
+ MachineClass *mc = MACHINE_CLASS(oc);
+
mc->desc = "or1k simulation";
mc->init = openrisc_sim_init;
mc->max_cpus = 2;
@@ -192,4 +206,16 @@ static void openrisc_sim_machine_init(MachineClass *mc)
mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200");
}
-DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init)
+static const TypeInfo or1ksim_machine_typeinfo = {
+ .name = TYPE_OR1KSIM_MACHINE,
+ .parent = TYPE_MACHINE,
+ .class_init = openrisc_sim_machine_init,
+ .instance_size = sizeof(Or1ksimState),
+};
+
+static void or1ksim_machine_init_register_types(void)
+{
+ type_register_static(&or1ksim_machine_typeinfo);
+}
+
+type_init(or1ksim_machine_init_register_types)
--
2.31.1
- [PULL v2 0/6] OpenRISC DTS Generation patches for 7.0, Stafford Horne, 2022/02/25
- [PULL v2 1/6] hw/openrisc/openrisc_sim: Create machine state for or1ksim,
Stafford Horne <=
- [PULL v2 2/6] hw/openrisc/openrisc_sim: Parameterize initialization, Stafford Horne, 2022/02/25
- [PULL v2 4/6] hw/openrisc/openrisc_sim: Increase max_cpus to 4, Stafford Horne, 2022/02/25
- [PULL v2 3/6] hw/openrisc/openrisc_sim: Use IRQ splitter when connecting UART, Stafford Horne, 2022/02/25
- [PULL v2 5/6] hw/openrisc/openrisc_sim: Add automatic device tree generation, Stafford Horne, 2022/02/25
- [PULL v2 6/6] hw/openrisc/openrisc_sim: Add support for initrd loading, Stafford Horne, 2022/02/25
- Re: [PULL v2 0/6] OpenRISC DTS Generation patches for 7.0, Peter Maydell, 2022/02/28