[PATCH 02/17] target/ppc: Use trace-events instead of CPU_LOG_INT

[Fabiano Rosas]

Part of our exception logging is using qemu_log_mask and part is using
trace-events. Move the remaining users of '-d int' to the trace-events
infrastructure.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
---
 target/ppc/excp_helper.c | 9 ++++++---
 target/ppc/misc_helper.c | 4 ++--
 target/ppc/trace-events  | 2 ++
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index dd1e9c20b9..2b5b1e00d8 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -19,6 +19,7 @@
 #include "qemu/osdep.h"
 #include "qemu/main-loop.h"
 #include "qemu/log.h"
+#include "qemu/error-report.h"
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "internal.h"
@@ -1599,9 +1600,11 @@ static void powerpc_excp(PowerPCCPU *cpu, int excp)
         cpu_abort(cs, "Invalid PowerPC exception %d. Aborting\n", excp);
     }
 
-    qemu_log_mask(CPU_LOG_INT, "Raise exception at " TARGET_FMT_lx
-                  " => %s (%d) error=%02x\n", env->nip, 
powerpc_excp_name(excp),
-                  excp, env->error_code);
+    if (qemu_loglevel_mask(CPU_LOG_INT)) {
+        warn_report_once("use -trace ppc_excp* instead of -d int\n");
+    }
+
+    trace_ppc_excp(env->nip, powerpc_excp_name(excp), excp, env->error_code);
 
     switch (env->excp_model) {
     case POWERPC_EXCP_40x:
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 06aa716cab..6bef03b154 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -27,6 +27,7 @@
 #include "mmu-book3s-v3.h"
 
 #include "helper_regs.h"
+#include "trace.h"
 
 /*****************************************************************************/
 /* SPR accesses */
@@ -47,8 +48,7 @@ static void raise_hv_fu_exception(CPUPPCState *env, uint32_t 
bit,
                                   const char *caller, uint32_t cause,
                                   uintptr_t raddr)
 {
-    qemu_log_mask(CPU_LOG_INT, "HV Facility %d is unavailable (%s)\n",
-                  bit, caller);
+    trace_ppc_excp_hv_fu(bit, caller);
 
     env->spr[SPR_HFSCR] &= ~((target_ulong)FSCR_IC_MASK << FSCR_IC_POS);
 
diff --git a/target/ppc/trace-events b/target/ppc/trace-events
index 0f6af7d73f..064b8f3e1f 100644
--- a/target/ppc/trace-events
+++ b/target/ppc/trace-events
@@ -38,3 +38,5 @@ ppc_excp_inval(uint64_t nip) "Invalid instruction at 0x%" 
PRIx64
 ppc_excp_print(const char *excp) "%s exception"
 ppc_excp_syscall(unsigned long r0, unsigned long r3, unsigned long r4, 
unsigned long r5, unsigned long r6, unsigned long r7, unsigned long r8, 
unsigned long nip) "r0=0x%016" PRIx64 " r3=0x%016" PRIx64 " r4=0x%016" PRIx64 " 
r5=0x%016" PRIx64 " r6=0x%016" PRIx64 " r7=0x%016" PRIx64 " r8=0x%016" PRIx64 " 
nip=0x%" PRIx64
 ppc_excp_hypercall(unsigned long r3, unsigned long r4, unsigned long r5, 
unsigned long r6, unsigned long r7, unsigned long r8, unsigned long r9, 
unsigned long r10, unsigned long nip) "r3=0x%016" PRIx64 " r4=0x%016" PRIx64 " 
r5=0x%016" PRIx64 " r6=0x%016" PRIx64 " r7=0x%016" PRIx64 " r8=0x%016" PRIx64 " 
r9=0x%016" PRIx64 " r10=0x%016" PRIx64 " nip=0x%" PRIx64
+ppc_excp_hv_fu(uint32_t bit, const char* caller) "HV Facility 0x%x is 
unavailable (%s)"
+ppc_excp(unsigned long nip, const char* name, int excp, uint32_t flags) "Raise 
exception at 0x%" PRIx64 " => %s (%d) error=0x%02x"
-- 
2.34.1