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Re: [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA)


From: Alex Bennée
Subject: Re: [PATCH v6 21/43] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing
Date: Wed, 02 Mar 2022 10:01:48 +0000
User-agent: mu4e 1.7.9; emacs 28.0.91

Jonathan Cameron <Jonathan.Cameron@huawei.com> writes:

> From: Ben Widawsky <ben.widawsky@intel.com>
>
> This should introduce no change. Subsequent work will make use of this
> new class member.
>
> Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  hw/cxl/cxl-mailbox-utils.c  |  3 +++
>  hw/mem/cxl_type3.c          | 24 +++++++++---------------
>  include/hw/cxl/cxl_device.h | 29 +++++++++++++++++++++++++++++
>  3 files changed, 41 insertions(+), 15 deletions(-)
>
> diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
> index d022711b2a..ccf9c3d794 100644
> --- a/hw/cxl/cxl-mailbox-utils.c
> +++ b/hw/cxl/cxl-mailbox-utils.c
> @@ -278,6 +278,8 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd 
> *cmd,
>      } __attribute__((packed)) *id;
>      _Static_assert(sizeof(*id) == 0x43, "Bad identify size");
>  
> +    CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
> +    CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
>      uint64_t size = cxl_dstate->pmem_size;
>  
>      if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
> @@ -292,6 +294,7 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd 
> *cmd,
>  
>      id->total_capacity = size / (256 << 20);
>      id->persistent_capacity = size / (256 << 20);
> +    id->lsa_size = cvc->get_lsa_size(ct3d);
>  
>      *len = sizeof(*id);
>      return CXL_MBOX_SUCCESS;
> diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
> index da091157f2..b16262d3cc 100644
> --- a/hw/mem/cxl_type3.c
> +++ b/hw/mem/cxl_type3.c
> @@ -13,21 +13,6 @@
>  #include "sysemu/hostmem.h"
>  #include "hw/cxl/cxl.h"
>  
> -typedef struct cxl_type3_dev {
> -    /* Private */
> -    PCIDevice parent_obj;
> -
> -    /* Properties */
> -    uint64_t size;
> -    HostMemoryBackend *hostmem;
> -
> -    /* State */
> -    CXLComponentState cxl_cstate;
> -    CXLDeviceState cxl_dstate;
> -} CXLType3Dev;
> -
> -#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
> -

If the structure had been in the header to start with it would be easier
to see the changes added for this bit.


>  static void build_dvsecs(CXLType3Dev *ct3d)
>  {
>      CXLComponentState *cxl_cstate = &ct3d->cxl_cstate;
> @@ -186,10 +171,16 @@ static Property ct3_props[] = {
>      DEFINE_PROP_END_OF_LIST(),
>  };
>  
> +static uint64_t get_lsa_size(CXLType3Dev *ct3d)
> +{
> +    return 0;
> +}
> +
>  static void ct3_class_init(ObjectClass *oc, void *data)
>  {
>      DeviceClass *dc = DEVICE_CLASS(oc);
>      PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
> +    CXLType3Class *cvc = CXL_TYPE3_DEV_CLASS(oc);
>  
>      pc->realize = ct3_realize;
>      pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
> @@ -201,11 +192,14 @@ static void ct3_class_init(ObjectClass *oc, void *data)
>      dc->desc = "CXL PMEM Device (Type 3)";
>      dc->reset = ct3d_reset;
>      device_class_set_props(dc, ct3_props);
> +
> +    cvc->get_lsa_size = get_lsa_size;
>  }
>  
>  static const TypeInfo ct3d_info = {
>      .name = TYPE_CXL_TYPE3_DEV,
>      .parent = TYPE_PCI_DEVICE,
> +    .class_size = sizeof(struct CXLType3Class),
>      .class_init = ct3_class_init,
>      .instance_size = sizeof(CXLType3Dev),
>      .instance_finalize = ct3_finalize,
> diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
> index 8102d2a813..ebb391153a 100644
> --- a/include/hw/cxl/cxl_device.h
> +++ b/include/hw/cxl/cxl_device.h
> @@ -230,4 +230,33 @@ REG64(CXL_MEM_DEV_STS, 0)
>      FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
>      FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
>  
> +typedef struct cxl_type3_dev {
> +    /* Private */
> +    PCIDevice parent_obj;
> +
> +    /* Properties */
> +    uint64_t size;
> +    HostMemoryBackend *hostmem;
> +    HostMemoryBackend *lsa;
> +
> +    /* State */
> +    CXLComponentState cxl_cstate;
> +    CXLDeviceState cxl_dstate;
> +} CXLType3Dev;
> +
> +#ifndef TYPE_CXL_TYPE3_DEV
> +#define TYPE_CXL_TYPE3_DEV "cxl-type3"
> +#endif
> +
> +#define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
> +OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV)
> +
> +struct CXLType3Class {
> +    /* Private */
> +    PCIDeviceClass parent_class;
> +
> +    /* public */
> +    uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
> +};
> +
>  #endif


-- 
Alex Bennée



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