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Re: [PATCH v3 4/5] hw/intc: Vectored Interrupt Controller (VIC)
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From: |
Peter Maydell |
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Subject: |
Re: [PATCH v3 4/5] hw/intc: Vectored Interrupt Controller (VIC) |
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Date: |
Fri, 4 Mar 2022 12:55:42 +0000 |
On Thu, 3 Mar 2022 at 15:39, Amir Gonnen <amir.gonnen@neuroblade.ai> wrote:
>
> Implement nios2 Vectored Interrupt Controller (VIC).
> VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi
> fields on Nios2CPU before raising an IRQ.
> For that purpose, VIC has a "cpu" property which should refer to the
> nios2 cpu and set by the board that connects VIC.
>
> Signed-off-by: Amir Gonnen <amir.gonnen@neuroblade.ai>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
- [PATCH v3 0/5] target/nios2: Shadow register set, EIC and VIC, Amir Gonnen, 2022/03/03
- [PATCH v3 1/5] target/nios2: Check supervisor on eret, Amir Gonnen, 2022/03/03
- [PATCH v3 3/5] target/nios2: Exteral Interrupt Controller (EIC), Amir Gonnen, 2022/03/03
- [PATCH v3 4/5] hw/intc: Vectored Interrupt Controller (VIC), Amir Gonnen, 2022/03/03
- Re: [PATCH v3 4/5] hw/intc: Vectored Interrupt Controller (VIC),
Peter Maydell <=
- [PATCH v3 5/5] hw/nios2: Machine with a Vectored Interrupt Controller, Amir Gonnen, 2022/03/03
- [PATCH v3 2/5] target/nios2: Shadow register set, Amir Gonnen, 2022/03/03