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Re: [PATCH 2/6] aspeed: Rework aspeed_board_init_flashes() interface
From: |
Alistair Francis |
Subject: |
Re: [PATCH 2/6] aspeed: Rework aspeed_board_init_flashes() interface |
Date: |
Tue, 8 Mar 2022 06:51:53 +1000 |
On Mon, Mar 7, 2022 at 5:24 PM Cédric Le Goater <clg@kaod.org> wrote:
>
> Currently, the allocation of the flash devices uses the number of
> slave selects configured in the SoC realize routine. It is simpler to
> use directly the number of FMC devices defined in the machine class
> and 1 for spi devices (which is what the SoC does in the back of the
> machine).
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/arm/aspeed.c | 11 +++++------
> 1 file changed, 5 insertions(+), 6 deletions(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 02918a594d24..be24508a9854 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -276,9 +276,8 @@ static void write_boot_rom(DriveInfo *dinfo, hwaddr addr,
> size_t rom_size,
> rom_add_blob_fixed("aspeed.boot_rom", storage, rom_size, addr);
> }
>
> -static void aspeed_board_init_flashes(AspeedSMCState *s,
> - const char *flashtype,
> - int unit0)
> +static void aspeed_board_init_flashes(AspeedSMCState *s, const char
> *flashtype,
> + int count, int unit0)
> {
> int i;
>
> @@ -286,7 +285,7 @@ static void aspeed_board_init_flashes(AspeedSMCState *s,
> return;
> }
>
> - for (i = 0; i < s->num_cs; ++i) {
> + for (i = 0; i < count; ++i) {
> DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i);
> qemu_irq cs_line;
> DeviceState *dev;
> @@ -382,10 +381,10 @@ static void aspeed_machine_init(MachineState *machine)
>
> aspeed_board_init_flashes(&bmc->soc.fmc,
> bmc->fmc_model ? bmc->fmc_model :
> amc->fmc_model,
> - 0);
> + amc->num_cs, 0);
> aspeed_board_init_flashes(&bmc->soc.spi[0],
> bmc->spi_model ? bmc->spi_model :
> amc->spi_model,
> - bmc->soc.fmc.num_cs);
> + 1, amc->num_cs);
>
> /* Install first FMC flash content as a boot rom. */
> if (drive0) {
> --
> 2.34.1
>
>
- Re: [PATCH 5/6] aspeed/smc: Let the SSI core layer define the bus name, (continued)