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[PATCH for-7.1 v6 08/51] target/nios2: Do not create TCGv for control re
From: |
Richard Henderson |
Subject: |
[PATCH for-7.1 v6 08/51] target/nios2: Do not create TCGv for control registers |
Date: |
Wed, 16 Mar 2022 22:04:55 -0700 |
We don't need to reference them often, and when we do it
is just as easy to load/store from cpu_env directly.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/nios2/translate.c | 33 ++++++++++++++++++++++++++-------
1 file changed, 26 insertions(+), 7 deletions(-)
diff --git a/target/nios2/translate.c b/target/nios2/translate.c
index 3f7bbd6d7b..e6e9a5ac6f 100644
--- a/target/nios2/translate.c
+++ b/target/nios2/translate.c
@@ -103,7 +103,7 @@ typedef struct DisasContext {
int mem_idx;
} DisasContext;
-static TCGv cpu_R[NUM_CORE_REGS];
+static TCGv cpu_R[NUM_GP_REGS];
static TCGv cpu_pc;
typedef struct Nios2Instruction {
@@ -394,7 +394,11 @@ static void eret(DisasContext *dc, uint32_t code, uint32_t
flags)
#ifdef CONFIG_USER_ONLY
g_assert_not_reached();
#else
- gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]);
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS]));
+ gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]);
+ tcg_temp_free(tmp);
+
dc->base.is_jmp = DISAS_NORETURN;
#endif
}
@@ -420,7 +424,11 @@ static void bret(DisasContext *dc, uint32_t code, uint32_t
flags)
#ifdef CONFIG_USER_ONLY
g_assert_not_reached();
#else
- gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]);
+ TCGv tmp = tcg_temp_new();
+ tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS]));
+ gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]);
+ tcg_temp_free(tmp);
+
dc->base.is_jmp = DISAS_NORETURN;
#endif
}
@@ -463,6 +471,7 @@ static void callr(DisasContext *dc, uint32_t code, uint32_t
flags)
static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags)
{
R_TYPE(instr, code);
+ TCGv t1, t2;
if (!gen_check_supervisor(dc)) {
return;
@@ -482,10 +491,19 @@ static void rdctl(DisasContext *dc, uint32_t code,
uint32_t flags)
* must perform the AND here, and anywhere else we need the
* guest value of ipending.
*/
- tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABLE]);
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+ tcg_gen_ld_tl(t1, cpu_env,
+ offsetof(CPUNios2State, regs[CR_IPENDING]));
+ tcg_gen_ld_tl(t2, cpu_env,
+ offsetof(CPUNios2State, regs[CR_IENABLE]));
+ tcg_gen_and_tl(cpu_R[instr.c], t1, t2);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
break;
default:
- tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]);
+ tcg_gen_ld_tl(cpu_R[instr.c], cpu_env,
+ offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
break;
}
}
@@ -522,7 +540,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint32_t
flags)
dc->base.is_jmp = DISAS_UPDATE;
/* fall through */
default:
- tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v);
+ tcg_gen_st_tl(v, cpu_env,
+ offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE]));
break;
}
#endif
@@ -909,7 +928,7 @@ void nios2_tcg_init(void)
{
int i;
- for (i = 0; i < NUM_CORE_REGS; i++) {
+ for (i = 0; i < NUM_GP_REGS; i++) {
cpu_R[i] = tcg_global_mem_new(cpu_env,
offsetof(CPUNios2State, regs[i]),
regnames[i]);
--
2.25.1
- [PATCH for-7.1 v6 00/51] target/nios2: Shadow register set, EIC and VIC, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 01/51] tcg: Fix indirect lowering vs TCG_OPF_COND_BRANCH, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 03/51] target/nios2: Stop generating code if gen_check_supervisor fails, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 02/51] target/nios2: Check supervisor on eret, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 04/51] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 06/51] target/nios2: Split out helper for eret instruction, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 05/51] target/nios2: Split PC out of env->regs[], Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 07/51] target/nios2: Fix BRET instruction, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 08/51] target/nios2: Do not create TCGv for control registers,
Richard Henderson <=
- [PATCH for-7.1 v6 10/51] target/nios2: Remove cpu_interrupts_enabled, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 09/51] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 11/51] target/nios2: Split control registers away from general registers, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 12/51] target/nios2: Clean up nios2_cpu_dump_state, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 13/51] target/nios2: Use hw/registerfields.h for CR_STATUS fields, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 14/51] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 15/51] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 16/51] target/nios2: Use hw/registerfields.h for CR_TLBACC fields, Richard Henderson, 2022/03/17
- [PATCH for-7.1 v6 17/51] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE, Richard Henderson, 2022/03/17