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[PULL 6/7] target/i386: properly reset TSC on reset
From: |
Paolo Bonzini |
Subject: |
[PULL 6/7] target/i386: properly reset TSC on reset |
Date: |
Fri, 25 Mar 2022 08:07:05 +0100 |
Some versions of Windows hang on reboot if their TSC value is greater
than 2^54. The calibration of the Hyper-V reference time overflows
and fails; as a result the processors' clock sources are out of sync.
The issue is that the TSC _should_ be reset to 0 on CPU reset and
QEMU tries to do that. However, KVM special cases writing 0 to the
TSC and thinks that QEMU is trying to hot-plug a CPU, which is
correct the first time through but not later. Thwart this valiant
effort and reset the TSC to 1 instead, but only if the CPU has been
run once.
For this to work, env->tsc has to be moved to the part of CPUArchState
that is not zeroed at the beginning of x86_cpu_reset.
Reported-by: Vadim Rozenfeld <vrozenfe@redhat.com>
Supersedes: <20220324082346.72180-1-pbonzini@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/cpu.c | 13 +++++++++++++
target/i386/cpu.h | 2 +-
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ec3b50bf6e..cb6b5467d0 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -5931,6 +5931,19 @@ static void x86_cpu_reset(DeviceState *dev)
env->xstate_bv = 0;
env->pat = 0x0007040600070406ULL;
+
+ if (kvm_enabled()) {
+ /*
+ * KVM handles TSC = 0 specially and thinks we are hot-plugging
+ * a new CPU, use 1 instead to force a reset.
+ */
+ if (env->tsc != 0) {
+ env->tsc = 1;
+ }
+ } else {
+ env->tsc = 0;
+ }
+
env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
if (env->features[FEAT_1_ECX] & CPUID_EXT_MONITOR) {
env->msr_ia32_misc_enable |= MSR_IA32_MISC_ENABLE_MWAIT;
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index e31e6bd8b8..982c532353 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1554,7 +1554,6 @@ typedef struct CPUArchState {
target_ulong kernelgsbase;
#endif
- uint64_t tsc;
uint64_t tsc_adjust;
uint64_t tsc_deadline;
uint64_t tsc_aux;
@@ -1708,6 +1707,7 @@ typedef struct CPUArchState {
int64_t tsc_khz;
int64_t user_tsc_khz; /* for sanity check only */
uint64_t apic_bus_freq;
+ uint64_t tsc;
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
void *xsave_buf;
uint32_t xsave_buf_len;
--
2.35.1
- [PULL 0/7] (Mostly) x86 fixes for QEMU 7.0.0-rc2, Paolo Bonzini, 2022/03/25
- [PULL 3/7] KVM: x86: workaround invalid CPUID[0xD, 9] info on some AMD processors, Paolo Bonzini, 2022/03/25
- [PULL 2/7] i386: Set MCG_STATUS_RIPV bit for mce SRAR error, Paolo Bonzini, 2022/03/25
- [PULL 1/7] target/i386/kvm: Free xsave_buf when destroying vCPU, Paolo Bonzini, 2022/03/25
- [PULL 7/7] build: disable fcf-protection on -march=486 -m16, Paolo Bonzini, 2022/03/25
- [PULL 4/7] configure: remove dead int128 test, Paolo Bonzini, 2022/03/25
- [PULL 6/7] target/i386: properly reset TSC on reset,
Paolo Bonzini <=
- [PULL 5/7] target/i386: tcg: high bits SSE cmp operation must be ignored, Paolo Bonzini, 2022/03/25
- Re: [PULL 0/7] (Mostly) x86 fixes for QEMU 7.0.0-rc2, Peter Maydell, 2022/03/25