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Re: [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v
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From: |
Alistair Francis |
|
Subject: |
Re: [PATCH 2/2] target/riscv: optimize helper for vmv<nr>r.v |
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Date: |
Mon, 28 Mar 2022 11:11:11 +1000 |
On Fri, Mar 25, 2022 at 7:01 PM Weiwei Li <liweiwei@iscas.ac.cn> wrote:
>
> LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmv<nr>r.v can share
> the same helper
>
> Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/helper.h | 5 +----
> target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++----------
> target/riscv/vector_helper.c | 29 ++++++++++---------------
> 3 files changed, 18 insertions(+), 33 deletions(-)
>
> diff --git a/target/riscv/helper.h b/target/riscv/helper.h
> index 26bbab2fab..a669d0187b 100644
> --- a/target/riscv/helper.h
> +++ b/target/riscv/helper.h
> @@ -1086,10 +1086,7 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, ptr,
> env, i32)
> DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32)
> DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32)
>
> -DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32)
> -DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32)
> +DEF_HELPER_4(vmvr_v, void, ptr, ptr, env, i32)
>
> DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32)
> DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2878ca3132..ec7c0e0d36 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -3695,7 +3695,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r
> *a)
> * Whole Vector Register Move Instructions ignore vtype and vl setting.
> * Thus, we don't need to check vill bit. (Section 16.6)
> */
> -#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \
> +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \
> static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \
> { \
> if (require_rvv(s) && \
> @@ -3710,13 +3710,8 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME *
> a) \
> } else { \
> TCGLabel *over = gen_new_label(); \
> tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \
> - \
> - static gen_helper_gvec_2_ptr * const fns[4] = { \
> - gen_helper_vmv1r_v, gen_helper_vmv2r_v, \
> - gen_helper_vmv4r_v, gen_helper_vmv8r_v, \
> - }; \
> tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \
> - cpu_env, maxsz, maxsz, 0, fns[SEQ]); \
> + cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v);
> \
> mark_vs_dirty(s); \
> gen_set_label(over); \
> } \
> @@ -3725,10 +3720,10 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME
> * a) \
> return false; \
> }
>
> -GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0)
> -GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1)
> -GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2)
> -GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3)
> +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1)
> +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2)
> +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4)
> +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8)
>
> static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
> {
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 3bd4aac9c9..1d4982ef7f 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -4888,25 +4888,18 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4)
> GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8)
>
> /* Vector Whole Register Move */
> -#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \
> -void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \
> - uint32_t desc) \
> -{ \
> - /* EEW = 8 */ \
> - uint32_t maxsz = simd_maxsz(desc); \
> - uint32_t i = env->vstart; \
> - \
> - memcpy((uint8_t *)vd + H1(i), \
> - (uint8_t *)vs2 + H1(i), \
> - maxsz - env->vstart); \
> - \
> - env->vstart = 0; \
> -}
> +void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc)
> +{
> + /* EEW = 8 */
> + uint32_t maxsz = simd_maxsz(desc);
> + uint32_t i = env->vstart;
> +
> + memcpy((uint8_t *)vd + H1(i),
> + (uint8_t *)vs2 + H1(i),
> + maxsz - env->vstart);
>
> -GEN_VEXT_VMV_WHOLE(vmv1r_v, 1)
> -GEN_VEXT_VMV_WHOLE(vmv2r_v, 2)
> -GEN_VEXT_VMV_WHOLE(vmv4r_v, 4)
> -GEN_VEXT_VMV_WHOLE(vmv8r_v, 8)
> + env->vstart = 0;
> +}
>
> /* Vector Integer Extension */
> #define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \
> --
> 2.17.1
>
>