Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

[Weiwei Li]

在 2022/3/30 下午6:02, eop Chen 写道:

Weiwei Li <liweiwei@iscas.ac.cn> 於 2022年3月30日 下午4:27 寫道：

在 2022/3/30 下午3:42, 陳約廷 写道:

Weiwei Li <liweiwei@iscas.ac.cn> 於 2022年3月28日 下午7:56 寫道：

在 2022/3/7 下午3:10, ~eopxd 写道:

From: eopXD <eop.chen@sifive.com>

Another question: max_elems is equal to total_elems when lmul >= 0.

So max_elems can be reused  here instead of caculating total_elems again.

I don’t understand your second question though. If nf = 3, there will be 3 registers

involved with the instruction (namely reg, reg+1, reg+2). Why do we care about

(reg+3)?

I just consider register group here. Reg, reg+1, reg+2 and reg+3 may belong to the same register group.

Regards,

Weiwei Li

According to v-spec (under section 7.8):

Each field will be held in successively numbered vector register groups. When EMUL>1

 each field will occupy a vector register group held in multiple successively numbered

vector registers, and the vector register group for each field must follow the usual vector

register alignment constraints (e.g., when EMUL=2 and NFIELDS=4, each field’s vector

register group must start at an even vector register, but does not have to start at a multiple

of 8 vector register number).

I think the spec has explained itself that NFIELDS represents the number of register groups involved

in this instruction. Therefore in a register group of 4 (LMUL = m2), NFIELD should be no more than 2.

The `vlmax` here would be (VLEN * 4 / EEW). In this sense, if the `vl` provided for the vector instruction

is within the range 2 * vlmax / 4 <= vl <= 3 * vlmax / 4, the elements in the 4th register (namely reg+3)

will all be counted as tail elements.

I hope this answers your question.

OK, Thanks a lot. This truly answers my question, even though what I really want to know is the case for EMUL=1, and NFIELDS=3.

since NFIELDS represents the number of register groups, not take the total of EMUL * NFIELDS into one register group ,

so reg+3 should not take into tail elements for my case.

Regards,

Weiwei Li

Regards,

eop Chen