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[PULL 2/2] target/riscv: rvv: Add missing early exit condition for whole
From: |
Alistair Francis |
Subject: |
[PULL 2/2] target/riscv: rvv: Add missing early exit condition for whole register load/store |
Date: |
Fri, 1 Apr 2022 09:44:41 +1000 |
From: "Yueh-Ting (eop) Chen" <eop.chen@sifive.com>
According to v-spec (section 7.9):
The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW,
regardless of current settings in vtype and vl. The usual property that no
elements are written if vstart ≥ vl does not apply to these instructions.
Instead, no elements are written if vstart ≥ evl.
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <164762720573.18409.3931931227997483525-0@git.sr.ht>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 275fded6e4..4ea7e41e1a 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1121,6 +1121,10 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1,
uint32_t nf,
gen_helper_ldst_whole *fn, DisasContext *s,
bool is_store)
{
+ uint32_t evl = (s->cfg_ptr->vlen / 8) * nf / (1 << s->sew);
+ TCGLabel *over = gen_new_label();
+ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, evl, over);
+
TCGv_ptr dest;
TCGv base;
TCGv_i32 desc;
@@ -1140,6 +1144,7 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1,
uint32_t nf,
if (!is_store) {
mark_vs_dirty(s);
}
+ gen_set_label(over);
return true;
}
--
2.35.1