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[PATCH v9 34/45] hw/cxl/component Add a dumb HDM decoder handler
From: |
Jonathan Cameron |
Subject: |
[PATCH v9 34/45] hw/cxl/component Add a dumb HDM decoder handler |
Date: |
Mon, 4 Apr 2022 16:14:34 +0100 |
From: Ben Widawsky <ben.widawsky@intel.com>
Add a trivial handler for now to cover the root bridge
where we could do some error checking in future.
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
hw/cxl/cxl-component-utils.c | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/hw/cxl/cxl-component-utils.c b/hw/cxl/cxl-component-utils.c
index 1a1adbd4cb..148f9f30d9 100644
--- a/hw/cxl/cxl-component-utils.c
+++ b/hw/cxl/cxl-component-utils.c
@@ -32,6 +32,31 @@ static uint64_t cxl_cache_mem_read_reg(void *opaque, hwaddr
offset,
}
}
+static void dumb_hdm_handler(CXLComponentState *cxl_cstate, hwaddr offset,
+ uint32_t value)
+{
+ ComponentRegisters *cregs = &cxl_cstate->crb;
+ uint32_t *cache_mem = cregs->cache_mem_registers;
+ bool should_commit = false;
+
+ switch (offset) {
+ case A_CXL_HDM_DECODER0_CTRL:
+ should_commit = FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT);
+ break;
+ default:
+ break;
+ }
+
+ memory_region_transaction_begin();
+ stl_le_p((uint8_t *)cache_mem + offset, value);
+ if (should_commit) {
+ ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0);
+ ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0);
+ ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1);
+ }
+ memory_region_transaction_commit();
+}
+
static void cxl_cache_mem_write_reg(void *opaque, hwaddr offset, uint64_t
value,
unsigned size)
{
@@ -45,6 +70,12 @@ static void cxl_cache_mem_write_reg(void *opaque, hwaddr
offset, uint64_t value,
}
if (cregs->special_ops && cregs->special_ops->write) {
cregs->special_ops->write(cxl_cstate, offset, value, size);
+ return;
+ }
+
+ if (offset >= A_CXL_HDM_DECODER_CAPABILITY &&
+ offset <= A_CXL_HDM_DECODER0_TARGET_LIST_HI) {
+ dumb_hdm_handler(cxl_cstate, offset, value);
} else {
cregs->cache_mem_registers[offset /
sizeof(*cregs->cache_mem_registers)] = value;
}
--
2.32.0
- [PATCH v9 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows., (continued)
- [PATCH v9 27/45] hw/cxl/host: Add support for CXL Fixed Memory Windows., Jonathan Cameron, 2022/04/04
- [PATCH v9 28/45] acpi/cxl: Introduce CFMWS structures in CEDT, Jonathan Cameron, 2022/04/04
- [PATCH v9 29/45] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Jonathan Cameron, 2022/04/04
- [PATCH v9 30/45] pci/pcie_port: Add pci_find_port_by_pn(), Jonathan Cameron, 2022/04/04
- [PATCH v9 31/45] CXL/cxl_component: Add cxl_get_hb_cstate(), Jonathan Cameron, 2022/04/04
- [PATCH v9 32/45] mem/cxl_type3: Add read and write functions for associated hostmem., Jonathan Cameron, 2022/04/04
- [PATCH v9 33/45] cxl/cxl-host: Add memops for CFMWS region., Jonathan Cameron, 2022/04/04
- [PATCH v9 34/45] hw/cxl/component Add a dumb HDM decoder handler,
Jonathan Cameron <=
- [PATCH v9 35/45] i386/pc: Enable CXL fixed memory windows, Jonathan Cameron, 2022/04/04
- [PATCH v9 36/45] tests/acpi: q35: Allow addition of a CXL test., Jonathan Cameron, 2022/04/04
- [PATCH v9 37/45] qtests/bios-tables-test: Add a test for CXL emulation., Jonathan Cameron, 2022/04/04
- [PATCH v9 38/45] tests/acpi: Add tables for CXL emulation., Jonathan Cameron, 2022/04/04
- [PATCH v9 39/45] qtest/cxl: Add more complex test cases with CFMWs, Jonathan Cameron, 2022/04/04
- [PATCH v9 40/45] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl, Jonathan Cameron, 2022/04/04
- [PATCH v9 41/45] qtest/cxl: Add aarch64 virt test for CXL, Jonathan Cameron, 2022/04/04
- [PATCH v9 42/45] docs/cxl: Add initial Compute eXpress Link (CXL) documentation., Jonathan Cameron, 2022/04/04
- [PATCH v9 43/45] pci-bridge/cxl_upstream: Add a CXL switch upstream port, Jonathan Cameron, 2022/04/04
- [PATCH v9 44/45] pci-bridge/cxl_downstream: Add a CXL switch downstream port, Jonathan Cameron, 2022/04/04