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Re: [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_
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From: |
Michael S. Tsirkin |
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Subject: |
Re: [RFC PATCH v1 1/1] include/hw/pci/pcie_host: Correct PCIE_MMCFG_BUS_MASK |
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Date: |
Mon, 11 Apr 2022 17:12:47 -0400 |
On Mon, Apr 11, 2022 at 09:38:18PM +0200, Francisco Iglesias wrote:
> According to [1] address bits 27 - 20 are mapped to the bus number (the
> TLPs bus number field is 8 bits).
>
> [1] PCI Express® Base Specification Revision 5.0 Version 1.0
>
> Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
> ---
> include/hw/pci/pcie_host.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h
> index 076457b270..b3c8ce973c 100644
> --- a/include/hw/pci/pcie_host.h
> +++ b/include/hw/pci/pcie_host.h
> @@ -60,7 +60,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
> /*
> * PCI express ECAM (Enhanced Configuration Address Mapping) format.
> * AKA mmcfg address
> - * bit 20 - 28: bus number
> + * bit 20 - 27: bus number
> * bit 15 - 19: device number
> * bit 12 - 14: function number
> * bit 0 - 11: offset in configuration space of a given device
this is correct, or to be more precise:
A[(20 + n – 1):20] and 1 <= n <= 8
> @@ -68,7 +68,7 @@ void pcie_host_mmcfg_update(PCIExpressHost *e,
> #define PCIE_MMCFG_SIZE_MAX (1ULL << 29)
> #define PCIE_MMCFG_SIZE_MIN (1ULL << 20)
> #define PCIE_MMCFG_BUS_BIT 20
> -#define PCIE_MMCFG_BUS_MASK 0x1ff
> +#define PCIE_MMCFG_BUS_MASK 0xff
> #define PCIE_MMCFG_DEVFN_BIT 12
> #define PCIE_MMCFG_DEVFN_MASK 0xff
> #define PCIE_MMCFG_CONFOFFSET_MASK 0xfff
> --
> 2.20.1