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[PATCH v2 13/24] target/arm: Enable SCR and HCR bits for RAS
From: |
Richard Henderson |
Subject: |
[PATCH v2 13/24] target/arm: Enable SCR and HCR bits for RAS |
Date: |
Mon, 11 Apr 2022 17:33:15 -0700 |
Enable writes to the TERR and TEA bits when RAS is enabled.
These bits are otherwise RES0.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b066a86f04..aa05a15e5c 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1765,6 +1765,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
}
valid_mask &= ~SCR_NET;
+ if (cpu_isar_feature(aa64_ras, cpu)) {
+ valid_mask |= SCR_TERR;
+ }
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= SCR_TLOR;
}
@@ -1779,6 +1782,9 @@ static void scr_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
}
} else {
valid_mask &= ~(SCR_RW | SCR_ST);
+ if (cpu_isar_feature(aa32_ras, cpu)) {
+ valid_mask |= SCR_TERR;
+ }
}
if (!arm_feature(env, ARM_FEATURE_EL2)) {
@@ -5289,6 +5295,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t
value, uint64_t valid_mask)
if (cpu_isar_feature(aa64_vh, cpu)) {
valid_mask |= HCR_E2H;
}
+ if (cpu_isar_feature(aa64_ras, cpu)) {
+ valid_mask |= HCR_TERR | HCR_TEA;
+ }
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= HCR_TLOR;
}
--
2.25.1
- [PATCH v2 23/24] target/arm: Define cortex-a76, (continued)
- [PATCH v2 23/24] target/arm: Define cortex-a76, Richard Henderson, 2022/04/11
- [PATCH v2 11/24] target/arm: Add isar_feature_{aa64,any}_ras, Richard Henderson, 2022/04/11
- [PATCH v2 09/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 06/24] target/arm: Split out arm32_max_features, Richard Henderson, 2022/04/11
- [PATCH v2 08/24] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/04/11
- [PATCH v2 12/24] target/arm: Add minimal RAS registers, Richard Henderson, 2022/04/11
- [PATCH v2 16/24] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 22/24] target/arm: Enable FEAT_DGH for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 17/24] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 24/24] target/arm: Define neoverse-n1, Richard Henderson, 2022/04/11
- [PATCH v2 13/24] target/arm: Enable SCR and HCR bits for RAS,
Richard Henderson <=
- [PATCH v2 18/24] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 19/24] target/arm: Update ISAR fields for ARMv8.8, Richard Henderson, 2022/04/11
- [PATCH v2 20/24] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/04/11
- [PATCH v2 21/24] target/arm: Enable FEAT_CSV3 for -cpu max, Richard Henderson, 2022/04/11