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[PATCH v3 00/60] target/arm: Cleanups, new features, new cpus
From: |
Richard Henderson |
Subject: |
[PATCH v3 00/60] target/arm: Cleanups, new features, new cpus |
Date: |
Sun, 17 Apr 2022 10:43:26 -0700 |
Supercedes: 20220412003326.588530-1-richard.henderson@linaro.org
("target/arm: 8 new features, A76 and N1")
Changes for v3:
* More field updates for H.a. This is not nearly complete, but what
I've encountered so far as I've begun implementing SME.
* Use bool instead of uint32_t for env->{aarch64,thumb}.
I had anticipated other changes for implementing PSTATE.{SM,FA},
but dropped those; these seemed like worth keeping.
* Use tcg_constant_* more -- got stuck on this while working on...
* Lots of cleanups to ARMCPRegInfo.
* Discard unreachable cpregs when ELx not available.
* Transform EL2 regs to RES0 when EL3 present but EL2 isn't.
This greatly simplifies registration of cpregs for new features.
Changes contextidr_el2, minimal_ras_reginfo, scxtnum_reginfo
within this patch set; other uses coming for SME.
r~
Richard Henderson (60):
tcg: Add tcg_constant_ptr
target/arm: Update ISAR fields for ARMv8.8
target/arm: Update SCR_EL3 bits to ARMv8.8
target/arm: Update SCTLR bits to ARMv9.2
target/arm: Change DisasContext.aarch64 to bool
target/arm: Change CPUArchState.aarch64 to bool
target/arm: Extend store_cpu_offset to take field size
target/arm: Change DisasContext.thumb to bool
target/arm: Change CPUArchState.thumb to bool
target/arm: Remove fpexc32_access
target/arm: Split out set_btype_raw
target/arm: Split out gen_rebuild_hflags
target/arm: Use tcg_constant in translate-a64.c
target/arm: Simplify GEN_SHIFT in translate.c
target/arm: Simplify gen_sar
target/arm: Simplify aa32 DISAS_WFI
target/arm: Use tcg_constant in translate.c
target/arm: Use tcg_constant in translate-m-nocp.c
target/arm: Use tcg_constant in translate-neon.c
target/arm: Use smin/smax for do_sat_addsub_32
target/arm: Use tcg_constant in translate-sve.c
target/arm: Use tcg_constant in translate-vfp.c
target/arm: Use tcg_constant_i32 in translate.h
target/arm: Split out cpregs.h
target/arm: Reorg CPAccessResult and access_check_cp_reg
target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h
target/arm: Make some more cpreg data static const
target/arm: Reorg ARMCPRegInfo type field bits
target/arm: Change cpreg access permissions to enum
target/arm: Name CPState type
target/arm: Name CPSecureState type
target/arm: Update sysreg fields when redirecting for E2H
target/arm: Store cpregs key in the hash table directly
target/arm: Cleanup add_cpreg_to_hashtable
target/arm: Handle cpreg registration for missing EL
target/arm: Drop EL3 no EL2 fallbacks
target/arm: Merge zcr reginfo
target/arm: Add isar predicates for FEAT_Debugv8p2
target/arm: Adjust definition of CONTEXTIDR_EL2
target/arm: Move cortex impdef sysregs to cpu_tcg.c
target/arm: Update qemu-system-arm -cpu max to cortex-a57
target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max
target/arm: Split out aa32_max_features
target/arm: Annotate arm_max_initfn with FEAT identifiers
target/arm: Use field names for manipulating EL2 and EL3 modes
target/arm: Enable FEAT_Debugv8p2 for -cpu max
target/arm: Enable FEAT_Debugv8p4 for -cpu max
target/arm: Add isar_feature_{aa64,any}_ras
target/arm: Add minimal RAS registers
target/arm: Enable SCR and HCR bits for RAS
target/arm: Implement virtual SError exceptions
target/arm: Implement ESB instruction
target/arm: Enable FEAT_RAS for -cpu max
target/arm: Enable FEAT_IESB for -cpu max
target/arm: Enable FEAT_CSV2 for -cpu max
target/arm: Enable FEAT_CSV2_2 for -cpu max
target/arm: Enable FEAT_CSV3 for -cpu max
target/arm: Enable FEAT_DGH for -cpu max
target/arm: Define cortex-a76
target/arm: Define neoverse-n1
docs/system/arm/emulation.rst | 10 +
docs/system/arm/virt.rst | 2 +
include/tcg/tcg.h | 2 +
target/arm/cpregs.h | 459 +++++++++++++++++
target/arm/cpu.h | 475 ++++--------------
target/arm/helper.h | 1 +
target/arm/internals.h | 16 +
target/arm/syndrome.h | 5 +
target/arm/translate-a32.h | 13 +-
target/arm/translate.h | 17 +-
target/arm/a32.decode | 16 +-
target/arm/t32.decode | 18 +-
hw/arm/pxa2xx.c | 2 +-
hw/arm/pxa2xx_pic.c | 2 +-
hw/arm/sbsa-ref.c | 2 +
hw/arm/virt.c | 2 +
hw/intc/arm_gicv3_cpuif.c | 6 +-
hw/intc/arm_gicv3_kvm.c | 3 +-
linux-user/arm/cpu_loop.c | 2 +-
target/arm/cpu.c | 88 ++--
target/arm/cpu64.c | 349 +++++++------
target/arm/cpu_tcg.c | 232 ++++++---
target/arm/gdbstub.c | 5 +-
target/arm/helper-a64.c | 4 +-
target/arm/helper.c | 897 ++++++++++++++++++----------------
target/arm/hvf/hvf.c | 2 +-
target/arm/m_helper.c | 6 +-
target/arm/op_helper.c | 113 +++--
target/arm/translate-a64.c | 395 ++++++---------
target/arm/translate-m-nocp.c | 12 +-
target/arm/translate-neon.c | 21 +-
target/arm/translate-sve.c | 207 +++-----
target/arm/translate-vfp.c | 76 +--
target/arm/translate.c | 400 +++++++--------
34 files changed, 2026 insertions(+), 1834 deletions(-)
create mode 100644 target/arm/cpregs.h
--
2.25.1
- [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus,
Richard Henderson <=
- [PATCH v3 02/60] target/arm: Update ISAR fields for ARMv8.8, Richard Henderson, 2022/04/17
- [PATCH v3 01/60] tcg: Add tcg_constant_ptr, Richard Henderson, 2022/04/17
- [PATCH v3 07/60] target/arm: Extend store_cpu_offset to take field size, Richard Henderson, 2022/04/17
- [PATCH v3 09/60] target/arm: Change CPUArchState.thumb to bool, Richard Henderson, 2022/04/17
- [PATCH v3 03/60] target/arm: Update SCR_EL3 bits to ARMv8.8, Richard Henderson, 2022/04/17