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[PATCH v3 58/60] target/arm: Enable FEAT_DGH for -cpu max
From: |
Richard Henderson |
Subject: |
[PATCH v3 58/60] target/arm: Enable FEAT_DGH for -cpu max |
Date: |
Sun, 17 Apr 2022 10:44:24 -0700 |
This extension concerns not merging memory access, which TCG does
not implement. Thus we can trivially enable this feature.
Add a comment to handle_hint for the DGH instruction, but no code.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v2: Update emulation.rst
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
target/arm/translate-a64.c | 1 +
3 files changed, 3 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index f75f0fc110..bc9cdda75a 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -16,6 +16,7 @@ the following architecture extensions:
- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2)
- FEAT_CSV2_2 (Cache speculation variant 2, version 2)
- FEAT_CSV3 (Cache speculation variant 3)
+- FEAT_DGH (Data gathering hint)
- FEAT_DIT (Data Independent Timing instructions)
- FEAT_DPB (DC CVAP instruction)
- FEAT_Debugv8p2 (Debug changes for v8.2)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 6139f51267..336a941acd 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */
t = FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */
t = FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */
+ t = FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */
t = FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */
cpu->isar.id_aa64isar1 = t;
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index fc0b3ebf44..b44ab3ecf3 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t insn,
break;
case 0b00100: /* SEV */
case 0b00101: /* SEVL */
+ case 0b00110: /* DGH */
/* we treat all as NOP at least for now */
break;
case 0b00111: /* XPACLRI */
--
2.25.1
- [PATCH v3 52/60] target/arm: Implement ESB instruction, (continued)
- [PATCH v3 52/60] target/arm: Implement ESB instruction, Richard Henderson, 2022/04/17
- [PATCH v3 53/60] target/arm: Enable FEAT_RAS for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 51/60] target/arm: Implement virtual SError exceptions, Richard Henderson, 2022/04/17
- [PATCH v3 54/60] target/arm: Enable FEAT_IESB for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 56/60] target/arm: Enable FEAT_CSV2_2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 57/60] target/arm: Enable FEAT_CSV3 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 55/60] target/arm: Enable FEAT_CSV2 for -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 58/60] target/arm: Enable FEAT_DGH for -cpu max,
Richard Henderson <=
- [PATCH v3 59/60] target/arm: Define cortex-a76, Richard Henderson, 2022/04/17
- [PATCH v3 60/60] target/arm: Define neoverse-n1, Richard Henderson, 2022/04/17
- Re: [PATCH v3 00/60] target/arm: Cleanups, new features, new cpus, Peter Maydell, 2022/04/22