Re: [PATCH v1 32/43] hw/loongarch: Add LoongArch ipi interrupt support(IPI)

[Richard Henderson]

On 4/15/22 02:40, Xiaojuan Yang wrote:
> +static const VMStateDescription vmstate_loongarch_ipi = {
> +    .name = TYPE_LOONGARCH_IPI,
> +    .version_id = 0,
> +    .minimum_version_id = 0,
> +    .fields = (VMStateField[]) {
> +        VMSTATE_END_OF_LIST()
> +    }

Why are there no fields here?  There's definitely state you should be saving.


> diff --git a/include/hw/intc/loongarch_ipi.h b/include/hw/intc/loongarch_ipi.h
> new file mode 100644
> index 0000000000..d57b0c6192
> --- /dev/null
> +++ b/include/hw/intc/loongarch_ipi.h
> @@ -0,0 +1,46 @@
> +/* SPDX-License-Identifier: GPL-2.0-or-later */
> +/*
> + * LoongArch ipi interrupt header files
> + *
> + * Copyright (C) 2021 Loongson Technology Corporation Limited
> + */
> +
> +#ifndef HW_LOONGARCH_IPI_H
> +#define HW_LOONGARCH_IPI_H
> +
> +#include "hw/sysbus.h"
> +
> +/* Mainy used by iocsr read and write */
> +#define SMP_IPI_MAILBOX      0x1000ULL
> +#define CORE_STATUS_OFF       0x0
> +#define CORE_EN_OFF           0x4
> +#define CORE_SET_OFF          0x8
> +#define CORE_CLEAR_OFF        0xc
> +#define CORE_BUF_20           0x20
> +#define CORE_BUF_28           0x28
> +#define CORE_BUF_30           0x30
> +#define CORE_BUF_38           0x38
> +#define IOCSR_IPI_SEND        0x40
> +
> +#define MAX_IPI_CORE_NUM      16

So... 16 cores, but...

> diff --git a/include/hw/loongarch/loongarch.h b/include/hw/loongarch/loongarch.h
> index ffe10edc65..a659be2a7f 100644
> --- a/include/hw/loongarch/loongarch.h
> +++ b/include/hw/loongarch/loongarch.h
> @@ -12,6 +12,7 @@
>   #include "qemu-common.h"
>   #include "hw/boards.h"
>   #include "qemu/queue.h"
> +#include "hw/intc/loongarch_ipi.h"
>   
>   #define LOONGARCH_MAX_VCPUS     4

... only 4 cpus.

>   
> @@ -41,6 +42,7 @@ struct LoongArchMachineState {
>       /*< private >*/
>       MachineState parent_obj;
>   
> +    IPICore ipi_core[MAX_IPI_CORE_NUM];

So why 16 cores here?


r~