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[PULL 05/61] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2
From: |
Peter Maydell |
Subject: |
[PULL 05/61] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2 |
Date: |
Fri, 22 Apr 2022 11:03:36 +0100 |
In a GICv3, it is impossible for the GIC to deliver a VIRQ or VFIQ to
the CPU unless the CPU has EL2, because VIRQ and VFIQ are only
configurable via EL2-only system registers. Moreover, in our
implementation we were only calculating and updating the state of the
VIRQ and VFIQ lines in gicv3_cpuif_virt_irq_fiq_update() when those
EL2 system registers changed. We were therefore able to assert in
arm_cpu_set_irq() that we didn't see a VIRQ or VFIQ line update if
EL2 wasn't present.
This assumption no longer holds with GICv4:
* even if the CPU does not have EL2 the guest is able to cause the
GIC to deliver a virtual LPI by programming the ITS (which is a
silly thing for it to do, but possible)
* because we now need to recalculate the state of the VIRQ and VFIQ
lines in more cases than just "some EL2 GIC sysreg was written",
we will see calls to arm_cpu_set_irq() for "VIRQ is 0, VFIQ is 0"
even if the guest is not using the virtual LPI parts of the ITS
Remove the assertions, and instead simply ignore the state of the
VIRQ and VFIQ lines if the CPU does not have EL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220408141550.1271295-6-peter.maydell@linaro.org
---
target/arm/cpu.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3609de08882..fa13fce355a 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -694,6 +694,16 @@ static void arm_cpu_set_irq(void *opaque, int irq, int
level)
[ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
};
+ if (!arm_feature(env, ARM_FEATURE_EL2) &&
+ (irq == ARM_CPU_VIRQ || irq == ARM_CPU_VFIQ)) {
+ /*
+ * The GIC might tell us about VIRQ and VFIQ state, but if we don't
+ * have EL2 support we don't care. (Unless the guest is doing something
+ * silly this will only be calls saying "level is still 0".)
+ */
+ return;
+ }
+
if (level) {
env->irq_line_state |= mask[irq];
} else {
@@ -702,11 +712,9 @@ static void arm_cpu_set_irq(void *opaque, int irq, int
level)
switch (irq) {
case ARM_CPU_VIRQ:
- assert(arm_feature(env, ARM_FEATURE_EL2));
arm_cpu_update_virq(cpu);
break;
case ARM_CPU_VFIQ:
- assert(arm_feature(env, ARM_FEATURE_EL2));
arm_cpu_update_vfiq(cpu);
break;
case ARM_CPU_IRQ:
--
2.25.1
- [PULL 00/61] target-arm queue, Peter Maydell, 2022/04/22
- [PULL 01/61] hw/intc/arm_gicv3_its: Add missing blank line, Peter Maydell, 2022/04/22
- [PULL 04/61] hw/intc/arm_gicv3: Report correct PIDR0 values for ID registers, Peter Maydell, 2022/04/22
- [PULL 07/61] hw/intc/arm_gicv3_its: Implement GITS_BASER2 for GICv4, Peter Maydell, 2022/04/22
- [PULL 12/61] hw/intc/arm_gicv3_its: Factor out CTE lookup sequence, Peter Maydell, 2022/04/22
- [PULL 10/61] hw/intc/arm_gicv3_its: Distinguish success and error cases of CMD_CONTINUE, Peter Maydell, 2022/04/22
- [PULL 05/61] target/arm/cpu.c: ignore VIRQ and VFIQ if no EL2,
Peter Maydell <=
- [PULL 06/61] hw/intc/arm_gicv3_its: Factor out "is intid a valid LPI ID?", Peter Maydell, 2022/04/22
- [PULL 09/61] hw/intc/arm_gicv3_its: Implement VMAPP, Peter Maydell, 2022/04/22
- [PULL 17/61] hw/intc/arm_gicv3_its: Implement VSYNC, Peter Maydell, 2022/04/22
- [PULL 15/61] hw/intc/arm_gicv3: Keep pointers to every connected ITS, Peter Maydell, 2022/04/22
- [PULL 03/61] hw/intc/arm_gicv3: Insist that redist region capacity matches CPU count, Peter Maydell, 2022/04/22
- [PULL 02/61] hw/intc/arm_gicv3: Sanity-check num-cpu property, Peter Maydell, 2022/04/22
- [PULL 08/61] hw/intc/arm_gicv3_its: Implement VMAPI and VMAPTI, Peter Maydell, 2022/04/22
- [PULL 11/61] hw/intc/arm_gicv3_its: Factor out "find ITE given devid, eventid", Peter Maydell, 2022/04/22
- [PULL 13/61] hw/intc/arm_gicv3_its: Split out process_its_cmd() physical interrupt code, Peter Maydell, 2022/04/22
- [PULL 19/61] hw/intc/arm_gicv3_its: Implement INV for virtual interrupts, Peter Maydell, 2022/04/22