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[PULL 55/61] target/arm: Simplify aa32 DISAS_WFI
From: |
Peter Maydell |
Subject: |
[PULL 55/61] target/arm: Simplify aa32 DISAS_WFI |
Date: |
Fri, 22 Apr 2022 11:04:26 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
The length of the previous insn may be computed from
the difference of start and end addresses.
Use tcg_constant_i32 while we're at it.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 12 ++++--------
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 086dc0d3b15..d09692c125b 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -9870,18 +9870,14 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase,
CPUState *cpu)
/* nothing more to generate */
break;
case DISAS_WFI:
- {
- TCGv_i32 tmp = tcg_const_i32((dc->thumb &&
- !(dc->insn & (1U << 31))) ? 2 : 4);
-
- gen_helper_wfi(cpu_env, tmp);
- tcg_temp_free_i32(tmp);
- /* The helper doesn't necessarily throw an exception, but we
+ gen_helper_wfi(cpu_env,
+ tcg_constant_i32(dc->base.pc_next - dc->pc_curr));
+ /*
+ * The helper doesn't necessarily throw an exception, but we
* must go back to the main loop to check for interrupts anyway.
*/
tcg_gen_exit_tb(NULL, 0);
break;
- }
case DISAS_WFE:
gen_helper_wfe(cpu_env);
break;
--
2.25.1
- [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity, (continued)
- [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity, Peter Maydell, 2022/04/22
- [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2, Peter Maydell, 2022/04/22
- [PULL 46/61] target/arm: Change CPUArchState.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 47/61] target/arm: Extend store_cpu_offset to take field size, Peter Maydell, 2022/04/22
- [PULL 49/61] target/arm: Change CPUArchState.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 50/61] target/arm: Remove fpexc32_access, Peter Maydell, 2022/04/22
- [PULL 51/61] target/arm: Split out set_btype_raw, Peter Maydell, 2022/04/22
- [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c, Peter Maydell, 2022/04/22
- [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI,
Peter Maydell <=
- [PULL 52/61] target/arm: Split out gen_rebuild_hflags, Peter Maydell, 2022/04/22
- [PULL 48/61] target/arm: Change DisasContext.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 54/61] target/arm: Simplify gen_sar, Peter Maydell, 2022/04/22
- [PULL 56/61] target/arm: Use tcg_constant in translate-m-nocp.c, Peter Maydell, 2022/04/22
- [PULL 57/61] target/arm: Use tcg_constant in translate-neon.c, Peter Maydell, 2022/04/22
- [PULL 61/61] hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate(), Peter Maydell, 2022/04/22
- [PULL 58/61] target/arm: Use smin/smax for do_sat_addsub_32, Peter Maydell, 2022/04/22
- [PULL 41/61] hw/arm/virt: Support TCG GICv4, Peter Maydell, 2022/04/22
- [PULL 59/61] target/arm: Use tcg_constant in translate-vfp.c, Peter Maydell, 2022/04/22
- [PULL 60/61] target/arm: Use tcg_constant_i32 in translate.h, Peter Maydell, 2022/04/22