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[PULL 48/61] target/arm: Change DisasContext.thumb to bool
From: |
Peter Maydell |
Subject: |
[PULL 48/61] target/arm: Change DisasContext.thumb to bool |
Date: |
Fri, 22 Apr 2022 11:04:19 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Bool is a more appropriate type for this value.
Move the member down in the struct to keep the
bool type members together and remove a hole.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.h | 2 +-
target/arm/translate-a64.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.h b/target/arm/translate.h
index 8b7dd1a4c05..050d80f6f90 100644
--- a/target/arm/translate.h
+++ b/target/arm/translate.h
@@ -30,7 +30,6 @@ typedef struct DisasContext {
bool eci_handled;
/* TCG op to rewind to if this turns out to be an invalid ECI state */
TCGOp *insn_eci_rewind;
- int thumb;
int sctlr_b;
MemOp be_data;
#if !defined(CONFIG_USER_ONLY)
@@ -65,6 +64,7 @@ typedef struct DisasContext {
GHashTable *cp_regs;
uint64_t features; /* CPU features bits */
bool aarch64;
+ bool thumb;
/* Because unallocated encodings generate different exception syndrome
* information from traps due to FP being disabled, we can't do a single
* "is fp access disabled" check at a high level in the decode tree.
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f6303848918..1ae465687ad 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -14670,7 +14670,7 @@ static void
aarch64_tr_init_disas_context(DisasContextBase *dcbase,
*/
dc->secure_routed_to_el3 = arm_feature(env, ARM_FEATURE_EL3) &&
!arm_el_is_aa64(env, 3);
- dc->thumb = 0;
+ dc->thumb = false;
dc->sctlr_b = 0;
dc->be_data = EX_TBFLAG_ANY(tb_flags, BE_DATA) ? MO_BE : MO_LE;
dc->condexec_mask = 0;
--
2.25.1
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, (continued)
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2, Peter Maydell, 2022/04/22
- [PULL 46/61] target/arm: Change CPUArchState.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 47/61] target/arm: Extend store_cpu_offset to take field size, Peter Maydell, 2022/04/22
- [PULL 49/61] target/arm: Change CPUArchState.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 50/61] target/arm: Remove fpexc32_access, Peter Maydell, 2022/04/22
- [PULL 51/61] target/arm: Split out set_btype_raw, Peter Maydell, 2022/04/22
- [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c, Peter Maydell, 2022/04/22
- [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI, Peter Maydell, 2022/04/22
- [PULL 52/61] target/arm: Split out gen_rebuild_hflags, Peter Maydell, 2022/04/22
- [PULL 48/61] target/arm: Change DisasContext.thumb to bool,
Peter Maydell <=
- [PULL 54/61] target/arm: Simplify gen_sar, Peter Maydell, 2022/04/22
- [PULL 56/61] target/arm: Use tcg_constant in translate-m-nocp.c, Peter Maydell, 2022/04/22
- [PULL 57/61] target/arm: Use tcg_constant in translate-neon.c, Peter Maydell, 2022/04/22
- [PULL 61/61] hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate(), Peter Maydell, 2022/04/22
- [PULL 58/61] target/arm: Use smin/smax for do_sat_addsub_32, Peter Maydell, 2022/04/22
- [PULL 41/61] hw/arm/virt: Support TCG GICv4, Peter Maydell, 2022/04/22
- [PULL 59/61] target/arm: Use tcg_constant in translate-vfp.c, Peter Maydell, 2022/04/22
- [PULL 60/61] target/arm: Use tcg_constant_i32 in translate.h, Peter Maydell, 2022/04/22
- Re: [PULL 00/61] target-arm queue, Richard Henderson, 2022/04/22