Re: [RFC PATCH 0/2] hw/riscv: Baseline QEMU support for RISC-V IOMMU (draft)

[Atish Patra]

On Wed, Apr 20, 2022 at 11:18 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Thu, Mar 17, 2022 at 8:23 AM Tomasz Jeznach <tjeznach@rivosinc.com> wrote:
> >
> > This is the series of patches to introduce RISC-V IOMMU emulation in QEMU.
> >
> > The Rivos IOMMU device implementation is based on a draft proposal of a
> > RISC-V I/O Management Unit (IOMMU) [1] as published on 2022/03/10, shared 
> > and
> > discussed with RISCV-V IOMMU Task Group [2].
>
> Awesome!
>
> >
> > Specification is in *draft* stage and is expected to be changed based on
> > discussion and feedback received from RISC-V IOMMU TG.
>
> So I'm assuming this will become a "RISC-V IOMMU" and not a "Rivos
> IOMMU" as the spec progresses?
>
> >
> > This series enables rivos-iommu support for riscv/virt machine emulation.
> > With corresponding Linux kernel driver and (modified) pending AIA-IMSIC
> > support [3] QEMU is able to boot into Linux with I/O protection enabled for
> > PCIe devices.  Without AIA-IMSIC support interrupt based I/O translation 
> > fault
> > reporting and MSI remapping features are not available, while all remaining
> > IOMMU features are active.
> >
> > To enable IOMMU in QEMU add 'rivos-iommu' to the device list for 'virt' 
> > machine
> > emulation.
>
> Cool!
>
> So one thought, if a user is expected to enable the IOMMU, AIA and
> other options in the virt machine it might be worthwhile adding a
> coverall option.
>
> So for example a user could do
>
> -machine virt,full-virt=true
>
> and that would enable the IOMMU, AIA and other important virtulisation 
> features.
>

There are different options for AIA as well. aplic , aplic-imsic. In
the future, there can be imsic
option as well depending on the fate of the 'minic' machine series.

I guess you mean aplic-imsic here.

>
> Alistair
>
> >
> >
> > [1] 
> > https://docs.google.com/document/d/1ytBZ6eDk1pAeBlZjDvm6_qqJbKQ0fMYKedyx0uoAGB0/view
> > [2] https://lists.riscv.org/g/tech-iommu/message/3
> > [3] 
> > https://lore.kernel.org/qemu-devel/20220220085526.808674-1-anup@brainfault.org
> >
> > Tomasz Jeznach (2):
> >   hw/riscv: rivos-iommu: Baseline implementation of RIVOS IOMMU.
> >   hw/riscv: virt: Add rivos-iommu device to 'virt' machine.
> >
> >  hw/riscv/Kconfig               |    4 +
> >  hw/riscv/meson.build           |    1 +
> >  hw/riscv/rivos_iommu.c         | 1350 ++++++++++++++++++++++++++++++++
> >  hw/riscv/trace-events          |    7 +
> >  hw/riscv/trace.h               |    2 +
> >  hw/riscv/virt.c                |  115 ++-
> >  include/hw/pci/pci_ids.h       |    1 +
> >  include/hw/riscv/rivos_iommu.h |   80 ++
> >  include/hw/riscv/virt.h        |    2 +
> >  meson.build                    |    1 +
> >  10 files changed, 1539 insertions(+), 24 deletions(-)
> >  create mode 100644 hw/riscv/rivos_iommu.c
> >  create mode 100644 hw/riscv/trace-events
> >  create mode 100644 hw/riscv/trace.h
> >  create mode 100644 include/hw/riscv/rivos_iommu.h
> >
> > --
> > 2.25.1
> >
> >
>


-- 
Regards,
Atish