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[PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floatin
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From: |
~eopxd |
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Subject: |
[PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions |
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Date: |
Mon, 25 Apr 2022 14:18:47 -0000 |
From: Yueh-Ting (eop) Chen <eop.chen@sifive.com>
Signed-off-by: eop Chen <eop.chen@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
---
target/riscv/insn_trans/trans_rvv.c.inc | 12 +++++++++
target/riscv/vector_helper.c | 36 +++++++++++++++++++++++++
2 files changed, 48 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index be08ec8a2e..e404d24bcf 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -2415,6 +2415,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2498,6 +2499,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2537,6 +2539,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2577,6 +2580,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2614,6 +2618,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs1), \
vreg_ofs(s, a->rs2), cpu_env, \
@@ -2654,6 +2659,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
return opfvf_trans(a->rd, a->rs1, a->rs2, data, \
fns[s->sew - 1], s); \
} \
@@ -2738,6 +2744,7 @@ static bool do_opfv(DisasContext *s, arg_rmr *a,
data = FIELD_DP32(data, VDATA, VM, a->vm);
data = FIELD_DP32(data, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0),
vreg_ofs(s, a->rs2), cpu_env,
s->cfg_ptr->vlen / 8,
@@ -2852,6 +2859,7 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f
*a)
TCGv_i32 desc;
uint32_t data = FIELD_DP32(0, VDATA, LMUL, s->lmul);
data = FIELD_DP32(data, VDATA, VTA, s->vta);
+ data = FIELD_DP32(data, VDATA, VMA, s->vma);
static gen_helper_vmv_vx * const fns[3] = {
gen_helper_vmv_v_x_h,
gen_helper_vmv_v_x_w,
@@ -2953,6 +2961,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3005,6 +3014,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3073,6 +3083,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
@@ -3127,6 +3138,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a)
\
\
data = FIELD_DP32(data, VDATA, VM, a->vm); \
data = FIELD_DP32(data, VDATA, VTA, s->vta); \
+ data = FIELD_DP32(data, VDATA, VMA, s->vma); \
tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \
vreg_ofs(s, a->rs2), cpu_env, \
s->cfg_ptr->vlen / 8, \
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index e266a8673c..0af65e5423 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -3051,10 +3051,16 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1,
\
uint32_t total_elems = \
vext_get_total_elems(desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, i, \
+ i * ESZ, \
+ (i + 1) * \
+ ESZ); \
continue; \
} \
do_##NAME(vd, vs1, vs2, i, env); \
@@ -3091,10 +3097,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1,
\
uint32_t total_elems = \
vext_get_total_elems(desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, i, \
+ i * ESZ, \
+ (i + 1) * \
+ ESZ); \
continue; \
} \
do_##NAME(vd, s1, vs2, i, env); \
@@ -3667,6 +3679,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t total_elems = \
vext_get_total_elems(desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
if (vl == 0) { \
@@ -3674,6 +3687,12 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
} \
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, \
+ i, \
+ i * ESZ, \
+ (i + 1) \
+ * ESZ); \
continue; \
} \
do_##NAME(vd, vs2, i, env); \
@@ -4188,12 +4207,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
*vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
@@ -4221,11 +4245,16 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void
*vs2, \
uint32_t esz = sizeof(ETYPE); \
uint32_t total_elems = vext_get_total_elems(desc, esz); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ if (vma) { \
+ vext_set_elem_mask(vd, i, 1); \
+ } \
continue; \
} \
vext_set_elem_mask(vd, i, \
@@ -4347,10 +4376,17 @@ void HELPER(NAME)(void *vd, void *v0, void *vs2, \
uint32_t total_elems = \
vext_get_total_elems(desc, ESZ); \
uint32_t vta = vext_vta(desc); \
+ uint32_t vma = vext_vma(desc); \
uint32_t i; \
\
for (i = env->vstart; i < vl; i++) { \
if (!vm && !vext_elem_mask(v0, i)) { \
+ /* set masked-off elements to 1s */ \
+ vext_set_elems_1s_fns[ctzl(ESZ)](vd, vma, \
+ i, \
+ i * ESZ, \
+ (i + 1) * \
+ ESZ); \
continue; \
} \
do_##NAME(vd, vs2, i); \
--
2.34.2
- [PATCH qemu 0/9] Add mask agnostic behavior for rvv instructions, ~eopxd, 2022/04/25
- [PATCH qemu 2/9] target/riscv: rvv: Add mask agnostic for vector load / store instructions, ~eopxd, 2022/04/25
- [PATCH qemu 8/9] target/riscv: rvv: Add mask agnostic for vector mask instructions, ~eopxd, 2022/04/25
- [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions, ~eopxd, 2022/04/25
- [PATCH qemu 5/9] target/riscv: rvv: Add mask agnostic for vector integer comparison instructions, ~eopxd, 2022/04/25
- [PATCH qemu 9/9] target/riscv: rvv: Add mask agnostic for vector permutation instructions, ~eopxd, 2022/04/25
- [PATCH qemu 4/9] target/riscv: rvv: Add mask agnostic for vector integer shift instructions, ~eopxd, 2022/04/25
- [PATCH qemu 3/9] target/riscv: rvv: Add mask agnostic for vx instructions, ~eopxd, 2022/04/25
- [PATCH qemu 7/9] target/riscv: rvv: Add mask agnostic for vector floating-point instructions,
~eopxd <=
- [PATCH qemu 6/9] target/riscv: rvv: Add mask agnostic for vector fix-point arithmetic instructions, ~eopxd, 2022/04/25