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Re: [PATCH v3 35/60] target/arm: Handle cpreg registration for missing E
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 35/60] target/arm: Handle cpreg registration for missing EL |
Date: |
Tue, 26 Apr 2022 10:40:19 +0100 |
On Fri, 22 Apr 2022 at 11:57, Peter Maydell <peter.maydell@linaro.org> wrote:
> Just because
> the architecture usually defines that an _EL2 register is
> RES0 if EL2 is not present doesn't mean that it does so for
> every register or that it guarantees that it will continue
> to do so in future. (For instance I found ZCR_EL2 and TFSR_EL2
> don't have that statement in their documentation, which might or
> might not be an oversight.)
In those two cases, it probably is a documentation omission.
-- PMM
- Re: [PATCH v3 31/60] target/arm: Name CPSecureState type, (continued)
- [PATCH v3 38/60] target/arm: Add isar predicates for FEAT_Debugv8p2, Richard Henderson, 2022/04/17
- [PATCH v3 39/60] target/arm: Adjust definition of CONTEXTIDR_EL2, Richard Henderson, 2022/04/17
- [PATCH v3 33/60] target/arm: Store cpregs key in the hash table directly, Richard Henderson, 2022/04/17
- [PATCH v3 36/60] target/arm: Drop EL3 no EL2 fallbacks, Richard Henderson, 2022/04/17
- [PATCH v3 34/60] target/arm: Cleanup add_cpreg_to_hashtable, Richard Henderson, 2022/04/17
- [PATCH v3 35/60] target/arm: Handle cpreg registration for missing EL, Richard Henderson, 2022/04/17
- [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Richard Henderson, 2022/04/17
- [PATCH v3 45/60] target/arm: Use field names for manipulating EL2 and EL3 modes, Richard Henderson, 2022/04/17
- [PATCH v3 42/60] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Richard Henderson, 2022/04/17
- [PATCH v3 41/60] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Richard Henderson, 2022/04/17
- [PATCH v3 43/60] target/arm: Split out aa32_max_features, Richard Henderson, 2022/04/17
- [PATCH v3 46/60] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Richard Henderson, 2022/04/17