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[PULL 04/54] target/arm: Use tcg_constant in gen_adc_CC
From: |
Peter Maydell |
Subject: |
[PULL 04/54] target/arm: Use tcg_constant in gen_adc_CC |
Date: |
Thu, 28 Apr 2022 15:39:08 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Note that tmp was doing double-duty as zero
and then later as a temporary in its own right.
Split the use of 0 to a new variable 'zero'.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate-a64.c | 26 +++++++++++++-------------
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b0b5e8b26d2..5c0fd897d6c 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -814,15 +814,15 @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0,
TCGv_i64 t1)
static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1)
{
if (sf) {
- TCGv_i64 result, cf_64, vf_64, tmp;
- result = tcg_temp_new_i64();
- cf_64 = tcg_temp_new_i64();
- vf_64 = tcg_temp_new_i64();
- tmp = tcg_const_i64(0);
+ TCGv_i64 result = tcg_temp_new_i64();
+ TCGv_i64 cf_64 = tcg_temp_new_i64();
+ TCGv_i64 vf_64 = tcg_temp_new_i64();
+ TCGv_i64 tmp = tcg_temp_new_i64();
+ TCGv_i64 zero = tcg_constant_i64(0);
tcg_gen_extu_i32_i64(cf_64, cpu_CF);
- tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp);
- tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp);
+ tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero);
+ tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero);
tcg_gen_extrl_i64_i32(cpu_CF, cf_64);
gen_set_NZ64(result);
@@ -838,15 +838,15 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64
t0, TCGv_i64 t1)
tcg_temp_free_i64(cf_64);
tcg_temp_free_i64(result);
} else {
- TCGv_i32 t0_32, t1_32, tmp;
- t0_32 = tcg_temp_new_i32();
- t1_32 = tcg_temp_new_i32();
- tmp = tcg_const_i32(0);
+ TCGv_i32 t0_32 = tcg_temp_new_i32();
+ TCGv_i32 t1_32 = tcg_temp_new_i32();
+ TCGv_i32 tmp = tcg_temp_new_i32();
+ TCGv_i32 zero = tcg_constant_i32(0);
tcg_gen_extrl_i64_i32(t0_32, t0);
tcg_gen_extrl_i64_i32(t1_32, t1);
- tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp);
- tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp);
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero);
+ tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero);
tcg_gen_mov_i32(cpu_ZF, cpu_NF);
tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32);
--
2.25.1
- [PULL 00/54] target-arm queue, Peter Maydell, 2022/04/28
- [PULL 02/54] target/arm: Use tcg_constant in gen_mte_check*, Peter Maydell, 2022/04/28
- [PULL 06/54] target/arm: Use tcg_constant in handle_sys, Peter Maydell, 2022/04/28
- [PULL 04/54] target/arm: Use tcg_constant in gen_adc_CC,
Peter Maydell <=
- [PULL 01/54] target/arm: Use tcg_constant in gen_probe_access, Peter Maydell, 2022/04/28
- [PULL 05/54] target/arm: Use tcg_constant in handle_msr_i, Peter Maydell, 2022/04/28
- [PULL 21/54] target/arm: Use tcg_constant in balance of translate-a64.c, Peter Maydell, 2022/04/28
- [PULL 24/54] target/arm: Use tcg_constant for gen_{msr,mrs}, Peter Maydell, 2022/04/28
- [PULL 07/54] target/arm: Use tcg_constant in disas_exc, Peter Maydell, 2022/04/28
- [PULL 15/54] target/arm: Use tcg_constant in handle_{rev16,crc32}, Peter Maydell, 2022/04/28
- [PULL 09/54] target/arm: Use tcg_constant in disas_ld_lit, Peter Maydell, 2022/04/28
- [PULL 11/54] target/arm: Use tcg_constant in disas_add_sum_imm*, Peter Maydell, 2022/04/28
- [PULL 13/54] target/arm: Use tcg_constant in shift_reg_imm, Peter Maydell, 2022/04/28
- [PULL 14/54] target/arm: Use tcg_constant in disas_cond_select, Peter Maydell, 2022/04/28