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[PULL 52/54] target/arm: Advertise support for FEAT_TTL
From: |
Peter Maydell |
Subject: |
[PULL 52/54] target/arm: Advertise support for FEAT_TTL |
Date: |
Thu, 28 Apr 2022 15:39:56 +0100 |
The Arm FEAT_TTL architectural feature allows the guest to provide an
optional hint in an AArch64 TLB invalidate operation about which
translation table level holds the leaf entry for the address being
invalidated. QEMU's TLB implementation doesn't need that hint, and
we correctly ignore the (previously RES0) bits in TLB invalidate
operation values that are now used for the TTL field. So we can
simply advertise support for it in our 'max' CPU.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220426160422.2353158-2-peter.maydell@linaro.org
---
docs/system/arm/emulation.rst | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst
index 520fd39071e..6ed2417f6fc 100644
--- a/docs/system/arm/emulation.rst
+++ b/docs/system/arm/emulation.rst
@@ -54,6 +54,7 @@ the following architecture extensions:
- FEAT_TLBIOS (TLB invalidate instructions in Outer Shareable domain)
- FEAT_TLBIRANGE (TLB invalidate range instructions)
- FEAT_TTCNP (Translation table Common not private translations)
+- FEAT_TTL (Translation Table Level)
- FEAT_TTST (Small translation tables)
- FEAT_UAO (Unprivileged Access Override control)
- FEAT_VHE (Virtualization Host Extensions)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index eb44c05822c..ec2d159163f 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -839,6 +839,7 @@ static void aarch64_max_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */
t = FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */
t = FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */
+ t = FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */
cpu->isar.id_aa64mmfr2 = t;
t = cpu->isar.id_aa64zfr0;
--
2.25.1
- [PULL 23/54] target/arm: Use tcg_constant for disas_iwmmxt_insn, (continued)
- [PULL 23/54] target/arm: Use tcg_constant for disas_iwmmxt_insn, Peter Maydell, 2022/04/28
- [PULL 22/54] target/arm: Use tcg_constant for aa32 exceptions, Peter Maydell, 2022/04/28
- [PULL 29/54] target/arm: Use tcg_constant for MOVW, UMAAL, CRC32, Peter Maydell, 2022/04/28
- [PULL 17/54] target/arm: Use tcg_constant in disas_fp*, Peter Maydell, 2022/04/28
- [PULL 34/54] target/arm: Use tcg_constant in trans_CPS_v7m, Peter Maydell, 2022/04/28
- [PULL 35/54] target/arm: Use tcg_constant in trans_CSEL, Peter Maydell, 2022/04/28
- [PULL 41/54] target/arm: Use tcg_constant in WHILE, Peter Maydell, 2022/04/28
- [PULL 37/54] target/arm: Use tcg_constant in SINCDEC, INCDEC, Peter Maydell, 2022/04/28
- [PULL 43/54] target/arm: Use tcg_constant in SUBR, Peter Maydell, 2022/04/28
- [PULL 44/54] target/arm: Use tcg_constant in do_zzi_{sat, ool}, do_fp_imm, Peter Maydell, 2022/04/28
- [PULL 52/54] target/arm: Advertise support for FEAT_TTL,
Peter Maydell <=
- [PULL 26/54] target/arm: Use tcg_constant for do_coproc_insn, Peter Maydell, 2022/04/28
- [PULL 39/54] target/arm: Use tcg_constant in {incr, wrap}_last_active, Peter Maydell, 2022/04/28
- [PULL 50/54] hw/arm/smmuv3: Cache event fault record, Peter Maydell, 2022/04/28
- [PULL 53/54] target/arm: Advertise support for FEAT_BBM level 2, Peter Maydell, 2022/04/28
- [PULL 32/54] target/arm: Use tcg_constant in LDM, STM, Peter Maydell, 2022/04/28
- [PULL 27/54] target/arm: Use tcg_constant for gen_srs, Peter Maydell, 2022/04/28
- [PULL 28/54] target/arm: Use tcg_constant for op_s_{rri,rxi}_rot, Peter Maydell, 2022/04/28
- [PULL 30/54] target/arm: Use tcg_constant for v7m MRS, MSR, Peter Maydell, 2022/04/28
- [PULL 33/54] target/arm: Use tcg_constant in CLRM, DLS, WLS, LE, Peter Maydell, 2022/04/28
- [PULL 40/54] target/arm: Use tcg_constant in do_clast_scalar, Peter Maydell, 2022/04/28