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[PULL 13/25] target/riscv: rvk: add support for sha512 related instructi
From: |
Alistair Francis |
Subject: |
[PULL 13/25] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension |
Date: |
Fri, 29 Apr 2022 14:31:07 +1000 |
From: Weiwei Li <liweiwei@iscas.ac.cn>
- add sha512sum0, sha512sig0, sha512sum1 and sha512sig1 instructions
Co-authored-by: Zewen Ye <lustrew@foxmail.com>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-11-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn32.decode | 5 +++
target/riscv/insn_trans/trans_rvk.c.inc | 53 +++++++++++++++++++++++++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 02a0c71890..d9ebb138d1 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -868,3 +868,8 @@ sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
+# *** RV64 Zknh Standard Extension ***
+sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
+sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
+sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
+sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
diff --git a/target/riscv/insn_trans/trans_rvk.c.inc
b/target/riscv/insn_trans/trans_rvk.c.inc
index 9ed057a153..8274b5a364 100644
--- a/target/riscv/insn_trans/trans_rvk.c.inc
+++ b/target/riscv/insn_trans/trans_rvk.c.inc
@@ -278,3 +278,56 @@ static bool trans_sha512sig1h(DisasContext *ctx,
arg_sha512sig1h *a)
REQUIRE_ZKNH(ctx);
return gen_sha512h_rv32(ctx, a, EXT_NONE, tcg_gen_rotli_i64, 3, 6, 19);
}
+
+static bool gen_sha512_rv64(DisasContext *ctx, arg_r2 *a, DisasExtend ext,
+ void (*func)(TCGv_i64, TCGv_i64, int64_t),
+ int64_t num1, int64_t num2, int64_t num3)
+{
+ TCGv dest = dest_gpr(ctx, a->rd);
+ TCGv src1 = get_gpr(ctx, a->rs1, ext);
+ TCGv_i64 t0 = tcg_temp_new_i64();
+ TCGv_i64 t1 = tcg_temp_new_i64();
+ TCGv_i64 t2 = tcg_temp_new_i64();
+
+ tcg_gen_extu_tl_i64(t0, src1);
+ tcg_gen_rotri_i64(t1, t0, num1);
+ tcg_gen_rotri_i64(t2, t0, num2);
+ tcg_gen_xor_i64(t1, t1, t2);
+ func(t2, t0, num3);
+ tcg_gen_xor_i64(t1, t1, t2);
+ tcg_gen_trunc_i64_tl(dest, t1);
+
+ gen_set_gpr(ctx, a->rd, dest);
+ tcg_temp_free_i64(t0);
+ tcg_temp_free_i64(t1);
+ tcg_temp_free_i64(t2);
+ return true;
+}
+
+static bool trans_sha512sig0(DisasContext *ctx, arg_sha512sig0 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 1, 8, 7);
+}
+
+static bool trans_sha512sig1(DisasContext *ctx, arg_sha512sig1 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_shri_i64, 19, 61, 6);
+}
+
+static bool trans_sha512sum0(DisasContext *ctx, arg_sha512sum0 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 28, 34, 39);
+}
+
+static bool trans_sha512sum1(DisasContext *ctx, arg_sha512sum1 *a)
+{
+ REQUIRE_64BIT(ctx);
+ REQUIRE_ZKNH(ctx);
+ return gen_sha512_rv64(ctx, a, EXT_NONE, tcg_gen_rotri_i64, 14, 18, 41);
+}
--
2.35.1
- [PULL 03/25] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values, (continued)
- [PULL 03/25] target/riscv: Support configuarable marchid, mvendorid, mipid CSR values, Alistair Francis, 2022/04/29
- [PULL 04/25] target/riscv: rvk: add cfg properties for zbk* and zk*, Alistair Francis, 2022/04/29
- [PULL 05/25] target/riscv: rvk: add support for zbkb extension, Alistair Francis, 2022/04/29
- [PULL 06/25] target/riscv: rvk: add support for zbkc extension, Alistair Francis, 2022/04/29
- [PULL 07/25] target/riscv: rvk: add support for zbkx extension, Alistair Francis, 2022/04/29
- [PULL 08/25] crypto: move sm4_sbox from target/arm, Alistair Francis, 2022/04/29
- [PULL 09/25] target/riscv: rvk: add support for zknd/zkne extension in RV32, Alistair Francis, 2022/04/29
- [PULL 10/25] target/riscv: rvk: add support for zkne/zknd extension in RV64, Alistair Francis, 2022/04/29
- [PULL 11/25] target/riscv: rvk: add support for sha256 related instructions in zknh extension, Alistair Francis, 2022/04/29
- [PULL 12/25] target/riscv: rvk: add support for sha512 related instructions for RV32 in zknh extension, Alistair Francis, 2022/04/29
- [PULL 13/25] target/riscv: rvk: add support for sha512 related instructions for RV64 in zknh extension,
Alistair Francis <=
- [PULL 14/25] target/riscv: rvk: add support for zksed/zksh extension, Alistair Francis, 2022/04/29
- [PULL 15/25] target/riscv: rvk: add CSR support for Zkr, Alistair Francis, 2022/04/29
- [PULL 16/25] disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions, Alistair Francis, 2022/04/29
- [PULL 17/25] target/riscv: rvk: expose zbk* and zk* properties, Alistair Francis, 2022/04/29
- [PULL 18/25] target/riscv: Fix incorrect PTE merge in walk_pte, Alistair Francis, 2022/04/29
- [PULL 19/25] target/riscv: add scalar crypto related extenstion strings to isa_string, Alistair Francis, 2022/04/29
- [PULL 20/25] hw/riscv: virt: Add a machine done notifier, Alistair Francis, 2022/04/29
- [PULL 21/25] hw/core: Move the ARM sysbus-fdt to core, Alistair Francis, 2022/04/29
- [PULL 22/25] hw/riscv: virt: Create a platform bus, Alistair Francis, 2022/04/29
- [PULL 23/25] hw/riscv: virt: Add support for generating platform FDT entries, Alistair Francis, 2022/04/29