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[PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOI
From: |
Xiaojuan Yang |
Subject: |
[PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC) |
Date: |
Fri, 29 Apr 2022 18:07:20 +0800 |
This patch realize the EIOINTC interrupt controller.
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
---
hw/intc/Kconfig | 3 +
hw/intc/loongarch_extioi.c | 248 +++++++++++++++++++++++++++++
hw/intc/meson.build | 1 +
hw/intc/trace-events | 5 +
hw/loongarch/Kconfig | 1 +
include/hw/intc/loongarch_extioi.h | 58 +++++++
6 files changed, 316 insertions(+)
create mode 100644 hw/intc/loongarch_extioi.c
create mode 100644 include/hw/intc/loongarch_extioi.h
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig
index 58f550b865..ecd2883ceb 100644
--- a/hw/intc/Kconfig
+++ b/hw/intc/Kconfig
@@ -99,3 +99,6 @@ config LOONGARCH_PCH_MSI
select MSI_NONBROKEN
bool
select UNIMP
+
+config LOONGARCH_EXTIOI
+ bool
diff --git a/hw/intc/loongarch_extioi.c b/hw/intc/loongarch_extioi.c
new file mode 100644
index 0000000000..6b49123512
--- /dev/null
+++ b/hw/intc/loongarch_extioi.c
@@ -0,0 +1,248 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Loongson 3A5000 ext interrupt controller emulation
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/module.h"
+#include "qemu/log.h"
+#include "hw/irq.h"
+#include "hw/sysbus.h"
+#include "hw/loongarch/virt.h"
+#include "hw/qdev-properties.h"
+#include "exec/address-spaces.h"
+#include "hw/intc/loongarch_extioi.h"
+#include "migration/vmstate.h"
+#include "trace.h"
+
+static void extioi_update_irq(LoongArchExtIOI *s, int irq_num, int level)
+{
+ int ipnum, cpu;
+
+ int ipmap_index = irq_num / 32 / 4;
+ int ipmap_offset = (irq_num / 32) & 0x3;
+ int ipmap_mask = 0xff << ipmap_offset;
+
+ int cpu_index = irq_num / 4;
+ int cpu_offset = irq_num & 0x3;
+ int cpu_mask = 0xff << ipmap_offset;
+
+ int coreisr_index = irq_num / 32;
+ int enable_index = coreisr_index;
+ int coreisr_mask = irq_num & 0x1f;
+ int enable_mask = coreisr_mask;
+ /*
+ * Routing in group of 32 interrupts.
+ * The default value of csr[0x420][49]
+ * is 0 and nobody will change it,
+ * so 'ipmap' use bitmap function.
+ */
+
+ ipnum = ((s->ipmap[ipmap_index] & ipmap_mask) >> ipmap_offset) & 0xf;
+ ipnum = ctz32(ipnum);
+ ipnum = (ipnum >= 4) ? 0 : ipnum;
+
+ cpu = ((s->coremap[cpu_index] & cpu_mask) >> cpu_offset) & 0xf;
+ cpu = ctz32(cpu);
+ cpu = (cpu >= 4) ? 0 : cpu;
+
+ if (level) {
+ /* if not enable return false */
+ if (((s->enable[enable_index]) & (1 << enable_mask)) == 0) {
+ return;
+ }
+ s->coreisr[cpu][coreisr_index] |= (1 << coreisr_mask);
+ qemu_set_irq(s->parent_irq[cpu][ipnum], level);
+ } else {
+ s->coreisr[cpu][coreisr_index] &= ~(1 << coreisr_mask);
+ qemu_set_irq(s->parent_irq[cpu][ipnum], level);
+ }
+}
+
+static void extioi_setirq(void *opaque, int irq, int level)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ trace_loongarch_extioi_setirq(irq, level);
+ extioi_update_irq(s, irq, level);
+}
+
+static uint64_t extioi_readw(void *opaque, hwaddr addr, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ unsigned long offset = addr & 0xffff;
+ uint32_t index, cpu, ret = 0;
+
+ switch (offset) {
+ case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
+ index = (offset - EXTIOI_NODETYPE_START) >> 2;
+ ret = s->nodetype[index];
+ break;
+ case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
+ index = (offset - EXTIOI_IPMAP_START) >> 2;
+ ret = s->ipmap[index];
+ break;
+ case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
+ index = (offset - EXTIOI_ENABLE_START) >> 2;
+ ret = s->enable[index];
+ break;
+ case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
+ index = (offset - EXTIOI_BOUNCE_START) >> 2;
+ ret = s->bounce[index];
+ break;
+ case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
+ index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
+ cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+ ret = s->coreisr[cpu][index];
+ break;
+ case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
+ index = (offset - EXTIOI_COREMAP_START) >> 2;
+ ret = s->coremap[index];
+ break;
+ default:
+ break;
+ }
+
+ trace_loongarch_extioi_readw((uint32_t)addr, ret);
+ return ret;
+}
+
+static void extioi_writew(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
+{
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(opaque);
+ int cpu, index, old_data, data_offset;
+ uint32_t offset;
+ trace_loongarch_extioi_writew(size, (uint32_t)addr, val);
+
+ offset = addr & 0xffff;
+
+ switch (offset) {
+ case EXTIOI_NODETYPE_START ... EXTIOI_NODETYPE_END - 1:
+ index = (offset - EXTIOI_NODETYPE_START) >> 2;
+ s->nodetype[index] = val;
+ break;
+ case EXTIOI_IPMAP_START ... EXTIOI_IPMAP_END - 1:
+ index = (offset - EXTIOI_IPMAP_START) >> 2;
+ s->ipmap[index] = val;
+ break;
+ case EXTIOI_ENABLE_START ... EXTIOI_ENABLE_END - 1:
+ index = (offset - EXTIOI_ENABLE_START) >> 2;
+ old_data = s->enable[index];
+ if (old_data != (int)val) {
+ s->enable[index] = val;
+ old_data = old_data ^ val;
+ data_offset = ctz32(old_data);
+ while (data_offset != 32) {
+ if (!(val & (1 << data_offset))) {
+ extioi_update_irq(s, data_offset + index * 32, 0);
+ }
+ old_data &= ~(1 << data_offset);
+ data_offset = ctz32(old_data);
+ }
+ }
+ break;
+ case EXTIOI_BOUNCE_START ... EXTIOI_BOUNCE_END - 1:
+ index = (offset - EXTIOI_BOUNCE_START) >> 2;
+ s->bounce[index] = val;
+ break;
+ case EXTIOI_COREISR_START ... EXTIOI_COREISR_END - 1:
+ index = ((offset - EXTIOI_COREISR_START) & 0x1f) >> 2;
+ cpu = ((offset - EXTIOI_COREISR_START) >> 8) & 0x3;
+ old_data = s->coreisr[cpu][index];
+ s->coreisr[cpu][index] = old_data & ~val;
+ if (old_data != s->coreisr[cpu][index]) {
+ data_offset = ctz32(val);
+ while (data_offset != 32) {
+ if ((old_data & (1 << data_offset))) {
+ extioi_update_irq(s, data_offset + index * 32, 0);
+ }
+ val &= ~(1 << data_offset);
+ data_offset = ctz32(val);
+ }
+ }
+ break;
+ case EXTIOI_COREMAP_START ... EXTIOI_COREMAP_END - 1:
+ index = (offset - EXTIOI_COREMAP_START) >> 2;
+ s->coremap[index] = val;
+ break;
+
+ default:
+ break;
+ }
+}
+
+static const MemoryRegionOps extioi_ops = {
+ .read = extioi_readw,
+ .write = extioi_writew,
+ .impl.min_access_size = 4,
+ .impl.max_access_size = 4,
+ .valid.min_access_size = 4,
+ .valid.max_access_size = 8,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+};
+
+static const VMStateDescription vmstate_loongarch_extioi = {
+ .name = TYPE_LOONGARCH_EXTIOI,
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(bounce, LoongArchExtIOI, EXTIOI_IRQS_GROUP_COUNT),
+ VMSTATE_UINT32_2DARRAY(coreisr, LoongArchExtIOI, LOONGARCH_MAX_VCPUS,
+ EXTIOI_IRQS_GROUP_COUNT),
+ VMSTATE_UINT32_ARRAY(nodetype, LoongArchExtIOI,
+ EXTIOI_IRQS_NODETYPE_COUNT / 2),
+ VMSTATE_UINT32_ARRAY(enable, LoongArchExtIOI, 8),
+ VMSTATE_UINT32_ARRAY(ipmap, LoongArchExtIOI, 2),
+ VMSTATE_UINT32_ARRAY(coremap, LoongArchExtIOI, EXTIOI_IRQS / 4),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void loongarch_extioi_instance_init(Object *obj)
+{
+ SysBusDevice *dev = SYS_BUS_DEVICE(obj);
+ LoongArchExtIOI *s = LOONGARCH_EXTIOI(obj);
+ int i, cpu, pin;
+
+ for (i = 0; i < EXTIOI_IRQS; i++) {
+ sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
+ }
+
+ qdev_init_gpio_in(DEVICE(obj), extioi_setirq, EXTIOI_IRQS);
+
+ for (cpu = 0; cpu < LOONGARCH_MAX_VCPUS; cpu++) {
+ memory_region_init_io(&s->extioi_iocsr_mem[cpu], OBJECT(s),
&extioi_ops,
+ s, "extioi_iocsr", 0x900);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_iocsr_mem[cpu]);
+ for (pin = 0; pin < LS3A_INTC_IP; pin++) {
+ qdev_init_gpio_out(DEVICE(obj), &s->parent_irq[cpu][pin], 1);
+ }
+ }
+ memory_region_init_io(&s->extioi_system_mem, OBJECT(s), &extioi_ops,
+ s, "extioi_system_mem", 0x900);
+ sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->extioi_system_mem);
+}
+
+static void loongarch_extioi_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+
+ dc->vmsd = &vmstate_loongarch_extioi;
+}
+
+static const TypeInfo loongarch_extioi_info = {
+ .name = TYPE_LOONGARCH_EXTIOI,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = loongarch_extioi_instance_init,
+ .instance_size = sizeof(struct LoongArchExtIOI),
+ .class_init = loongarch_extioi_class_init,
+};
+
+static void loongarch_extioi_register_types(void)
+{
+ type_register_static(&loongarch_extioi_info);
+}
+
+type_init(loongarch_extioi_register_types)
diff --git a/hw/intc/meson.build b/hw/intc/meson.build
index 1d407c046d..bcbf22ff51 100644
--- a/hw/intc/meson.build
+++ b/hw/intc/meson.build
@@ -66,3 +66,4 @@ specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true:
files('nios2_vic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_IPI', if_true:
files('loongarch_ipi.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_PIC', if_true:
files('loongarch_pch_pic.c'))
specific_ss.add(when: 'CONFIG_LOONGARCH_PCH_MSI', if_true:
files('loongarch_pch_msi.c'))
+specific_ss.add(when: 'CONFIG_LOONGARCH_EXTIOI', if_true:
files('loongarch_extioi.c'))
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 8bcc1b6992..2069cda51d 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -303,3 +303,8 @@ loongarch_pch_pic_writeb(unsigned size, uint32_t addr,
unsigned long val) "size:
# loongarch_pch_msi.c
loongarch_msi_set_irq(int irq_num) "set msi irq %d"
+
+# loongarch_extioi.c
+loongarch_extioi_setirq(int irq, int level) "set extirq irq %d level %d"
+loongarch_extioi_readw(uint32_t addr, uint32_t val) "addr: 0x%"PRIx32 "val:
0x%" PRIx32
+loongarch_extioi_writew(unsigned size, uint32_t addr, uint32_t val) "size: %u
addr: 0x%"PRIx32 "val: 0x%" PRIx32
diff --git a/hw/loongarch/Kconfig b/hw/loongarch/Kconfig
index d814fc6103..f779087416 100644
--- a/hw/loongarch/Kconfig
+++ b/hw/loongarch/Kconfig
@@ -5,3 +5,4 @@ config LOONGARCH_VIRT
select LOONGARCH_IPI
select LOONGARCH_PCH_PIC
select LOONGARCH_PCH_MSI
+ select LOONGARCH_EXTIOI
diff --git a/include/hw/intc/loongarch_extioi.h
b/include/hw/intc/loongarch_extioi.h
new file mode 100644
index 0000000000..b7057bbc34
--- /dev/null
+++ b/include/hw/intc/loongarch_extioi.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * LoongArch 3A5000 ext interrupt controller definitions
+ *
+ * Copyright (C) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "hw/sysbus.h"
+#include "hw/loongarch/virt.h"
+
+#ifndef LOONGARCH_EXTIOI_H
+#define LOONGARCH_EXTIOI_H
+
+#define LS3A_INTC_IP 8
+#define EXTIOI_IRQS (256)
+#define EXTIOI_IRQS_BITMAP_SIZE (256 / 8)
+/* map to ipnum per 32 irqs */
+#define EXTIOI_IRQS_IPMAP_SIZE (256 / 32)
+#define EXTIOI_IRQS_COREMAP_SIZE 256
+#define EXTIOI_IRQS_NODETYPE_COUNT 16
+#define EXTIOI_IRQS_GROUP_COUNT 8
+
+#define APIC_OFFSET 0x400
+#define APIC_BASE (0x1000ULL + APIC_OFFSET)
+
+#define EXTIOI_NODETYPE_START (0x4a0 - APIC_OFFSET)
+#define EXTIOI_NODETYPE_END (0x4c0 - APIC_OFFSET)
+#define EXTIOI_IPMAP_START (0x4c0 - APIC_OFFSET)
+#define EXTIOI_IPMAP_END (0x4c8 - APIC_OFFSET)
+#define EXTIOI_ENABLE_START (0x600 - APIC_OFFSET)
+#define EXTIOI_ENABLE_END (0x620 - APIC_OFFSET)
+#define EXTIOI_BOUNCE_START (0x680 - APIC_OFFSET)
+#define EXTIOI_BOUNCE_END (0x6a0 - APIC_OFFSET)
+#define EXTIOI_ISR_START (0x700 - APIC_OFFSET)
+#define EXTIOI_ISR_END (0x720 - APIC_OFFSET)
+#define EXTIOI_COREISR_START (0x800 - APIC_OFFSET)
+#define EXTIOI_COREISR_END (0xB20 - APIC_OFFSET)
+#define EXTIOI_COREMAP_START (0xC00 - APIC_OFFSET)
+#define EXTIOI_COREMAP_END (0xD00 - APIC_OFFSET)
+
+#define EXTIOI_SYSTEM_MEM 0x1fe01400
+#define TYPE_LOONGARCH_EXTIOI "loongarch.extioi"
+OBJECT_DECLARE_SIMPLE_TYPE(LoongArchExtIOI, LOONGARCH_EXTIOI)
+struct LoongArchExtIOI {
+ SysBusDevice parent_obj;
+ /* hardware state */
+ uint32_t nodetype[EXTIOI_IRQS_NODETYPE_COUNT / 2];
+ uint32_t bounce[EXTIOI_IRQS_GROUP_COUNT];
+ uint32_t coreisr[LOONGARCH_MAX_VCPUS][EXTIOI_IRQS_GROUP_COUNT];
+ uint32_t enable[8];
+ uint32_t ipmap[2];
+ uint32_t coremap[EXTIOI_IRQS / 4];
+ qemu_irq parent_irq[LOONGARCH_MAX_VCPUS][LS3A_INTC_IP];
+ qemu_irq irq[EXTIOI_IRQS];
+ MemoryRegion extioi_iocsr_mem[LOONGARCH_MAX_VCPUS];
+ MemoryRegion extioi_system_mem;
+};
+#endif /* LOONGARCH_EXTIOI_H */
--
2.31.1
- [PATCH v3 03/43] target/loongarch: Add main translation routines, (continued)
- [PATCH v3 03/43] target/loongarch: Add main translation routines, Xiaojuan Yang, 2022/04/29
- [PATCH v3 10/43] target/loongarch: Add floating point arithmetic instruction translation, Xiaojuan Yang, 2022/04/29
- [PATCH v3 13/43] target/loongarch: Add floating point move instruction translation, Xiaojuan Yang, 2022/04/29
- [PATCH v3 12/43] target/loongarch: Add floating point conversion instruction translation, Xiaojuan Yang, 2022/04/29
- [PATCH v3 14/43] target/loongarch: Add floating point load/store instruction translation, Xiaojuan Yang, 2022/04/29
- [PATCH v3 11/43] target/loongarch: Add floating point comparison instruction translation, Xiaojuan Yang, 2022/04/29
- [PATCH v3 16/43] target/loongarch: Add disassembler, Xiaojuan Yang, 2022/04/29
- [PATCH v3 37/43] hw/loongarch: Add some devices support for 3A5000., Xiaojuan Yang, 2022/04/29
- [PATCH v3 24/43] target/loongarch: Add constant timer support, Xiaojuan Yang, 2022/04/29
- [PATCH v3 30/43] hw/loongarch: Add support loongson3 virt machine type., Xiaojuan Yang, 2022/04/29
- [PATCH v3 34/43] hw/intc: Add LoongArch extioi interrupt controller(EIOINTC),
Xiaojuan Yang <=
- [PATCH v3 32/43] hw/intc: Add LoongArch ls7a interrupt controller support(PCH-PIC), Xiaojuan Yang, 2022/04/29
- [PATCH v3 40/43] hw/loongarch: Add LoongArch ls7a acpi device support, Xiaojuan Yang, 2022/04/29
- [PATCH v3 15/43] target/loongarch: Add branch instruction translation, Xiaojuan Yang, 2022/04/29
- [PATCH v3 18/43] target/loongarch: Add system emulation introduction, Xiaojuan Yang, 2022/04/29
- [PATCH v3 21/43] target/loongarch: Implement qmp_query_cpu_definitions(), Xiaojuan Yang, 2022/04/29
- [PATCH v3 33/43] hw/intc: Add LoongArch ls7a msi interrupt controller support(PCH-MSI), Xiaojuan Yang, 2022/04/29
- [PATCH v3 39/43] hw/loongarch: Add LoongArch load elf function., Xiaojuan Yang, 2022/04/29
- [PATCH v3 42/43] tests/tcg/loongarch64: Add hello/memory test in loongarch64 system, Xiaojuan Yang, 2022/04/29
- [PATCH v3 43/43] target/loongarch: 'make check-tcg' support, Xiaojuan Yang, 2022/04/29