Re: [PULL 00/25] riscv-to-apply queue

[Richard Henderson]

On 4/28/22 21:30, Alistair Francis wrote:
> From: Alistair Francis <alistair.francis@wdc.com>
>
> The following changes since commit f22833602095b05733bceaddeb20f3edfced3c07:
>
>    Merge tag 'pull-target-arm-20220428' of 
> https://git.linaro.org/people/pmaydell/qemu-arm into staging (2022-04-28 
> 08:34:17 -0700)
>
> are available in the Git repository at:
>
>    git@github.com:alistair23/qemu.git tags/pull-riscv-to-apply-20220429
>
> for you to fetch changes up to 325b7c4e7582c229d28c47123c3b986ed948eb84:
>
>    hw/riscv: Enable TPM backends (2022-04-29 10:48:48 +1000)
>
> ----------------------------------------------------------------
> Second RISC-V PR for QEMU 7.1
>
>   * Improve device tree generation
>   * Support configuarable marchid, mvendorid, mipid CSR values
>   * Add support for the Zbkb, Zbkc, Zbkx, Zknd/Zkne, Zknh, Zksed/Zksh and Zkr 
> extensions
>   * Fix incorrect PTE merge in walk_pte
>   * Add TPM support to the virt board

Applied, thanks.  Please update https://wiki.qemu.org/ChangeLog/7.1 as 
appropriate.


r~


> ----------------------------------------------------------------
> Alistair Francis (6):
>        hw/riscv: virt: Add a machine done notifier
>        hw/core: Move the ARM sysbus-fdt to core
>        hw/riscv: virt: Create a platform bus
>        hw/riscv: virt: Add support for generating platform FDT entries
>        hw/riscv: virt: Add device plug support
>        hw/riscv: Enable TPM backends
>
> Bin Meng (2):
>        hw/riscv: spike: Add '/chosen/stdout-path' in device tree unconditionally
>        hw/riscv: Don't add empty bootargs to device tree
>
> Frank Chang (1):
>        target/riscv: Support configuarable marchid, mvendorid, mipid CSR values
>
> Ralf Ramsauer (1):
>        target/riscv: Fix incorrect PTE merge in walk_pte
>
> Weiwei Li (15):
>        target/riscv: rvk: add cfg properties for zbk* and zk*
>        target/riscv: rvk: add support for zbkb extension
>        target/riscv: rvk: add support for zbkc extension
>        target/riscv: rvk: add support for zbkx extension
>        crypto: move sm4_sbox from target/arm
>        target/riscv: rvk: add support for zknd/zkne extension in RV32
>        target/riscv: rvk: add support for zkne/zknd extension in RV64
>        target/riscv: rvk: add support for sha256 related instructions in zknh 
> extension
>        target/riscv: rvk: add support for sha512 related instructions for RV32 
> in zknh extension
>        target/riscv: rvk: add support for sha512 related instructions for RV64 
> in zknh extension
>        target/riscv: rvk: add support for zksed/zksh extension
>        target/riscv: rvk: add CSR support for Zkr
>        disas/riscv.c: rvk: add disas support for Zbk* and Zk* instructions
>        target/riscv: rvk: expose zbk* and zk* properties
>        target/riscv: add scalar crypto related extenstion strings to isa_string
>
>   docs/system/riscv/virt.rst              |  20 ++
>   include/crypto/sm4.h                    |   6 +
>   include/hw/{arm => core}/sysbus-fdt.h   |   0
>   include/hw/riscv/virt.h                 |   8 +-
>   target/riscv/cpu.h                      |  17 ++
>   target/riscv/cpu_bits.h                 |   9 +
>   target/riscv/helper.h                   |  22 ++
>   target/riscv/pmp.h                      |   8 +-
>   target/riscv/insn32.decode              |  97 ++++++--
>   crypto/sm4.c                            |  49 ++++
>   disas/riscv.c                           | 173 +++++++++++++-
>   hw/arm/virt.c                           |   2 +-
>   hw/arm/xlnx-versal-virt.c               |   1 -
>   hw/{arm => core}/sysbus-fdt.c           |   2 +-
>   hw/riscv/microchip_pfsoc.c              |   2 +-
>   hw/riscv/sifive_u.c                     |   2 +-
>   hw/riscv/spike.c                        |   7 +-
>   hw/riscv/virt.c                         | 319 +++++++++++++++++---------
>   target/arm/crypto_helper.c              |  36 +--
>   target/riscv/bitmanip_helper.c          |  80 +++++++
>   target/riscv/cpu.c                      |  58 +++++
>   target/riscv/crypto_helper.c            | 302 ++++++++++++++++++++++++
>   target/riscv/csr.c                      | 118 +++++++++-
>   target/riscv/monitor.c                  |  11 +-
>   target/riscv/op_helper.c                |   9 +
>   target/riscv/translate.c                |   8 +
>   target/riscv/insn_trans/trans_rvb.c.inc | 116 ++++++++--
>   target/riscv/insn_trans/trans_rvk.c.inc | 391 ++++++++++++++++++++++++++++++++
>   crypto/meson.build                      |   1 +
>   hw/arm/meson.build                      |   1 -
>   hw/core/meson.build                     |   1 +
>   hw/riscv/Kconfig                        |   2 +
>   target/riscv/meson.build                |   3 +-
>   33 files changed, 1682 insertions(+), 199 deletions(-)
>   create mode 100644 include/crypto/sm4.h
>   rename include/hw/{arm => core}/sysbus-fdt.h (100%)
>   create mode 100644 crypto/sm4.c
>   rename hw/{arm => core}/sysbus-fdt.c (99%)
>   create mode 100644 target/riscv/crypto_helper.c
>   create mode 100644 target/riscv/insn_trans/trans_rvk.c.inc