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[PULL 04/32] target/arm: Merge zcr reginfo
From: |
Peter Maydell |
Subject: |
[PULL 04/32] target/arm: Merge zcr reginfo |
Date: |
Mon, 9 May 2022 12:58:20 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 55 ++++++++++++++-------------------------------
1 file changed, 17 insertions(+), 38 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ea2788b3d53..72d05070f02 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6122,35 +6122,22 @@ static void zcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
-static const ARMCPRegInfo zcr_el1_reginfo = {
- .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_SVE,
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
- .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_el2_reginfo = {
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_SVE,
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
- .writefn = zcr_write, .raw_writefn = raw_write
-};
-
-static const ARMCPRegInfo zcr_no_el2_reginfo = {
- .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_SVE,
- .readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
-};
-
-static const ARMCPRegInfo zcr_el3_reginfo = {
- .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
- .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL3_RW, .type = ARM_CP_SVE,
- .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
- .writefn = zcr_write, .raw_writefn = raw_write
+static const ARMCPRegInfo zcr_reginfo[] = {
+ { .name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
+ .access = PL1_RW, .type = ARM_CP_SVE,
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
+ .writefn = zcr_write, .raw_writefn = raw_write },
+ { .name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
+ .access = PL2_RW, .type = ARM_CP_SVE,
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
+ .writefn = zcr_write, .raw_writefn = raw_write },
+ { .name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
+ .access = PL3_RW, .type = ARM_CP_SVE,
+ .fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
+ .writefn = zcr_write, .raw_writefn = raw_write },
};
void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -8233,15 +8220,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
if (cpu_isar_feature(aa64_sve, cpu)) {
- define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
- if (arm_feature(env, ARM_FEATURE_EL2)) {
- define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
- } else {
- define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
- }
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
- }
+ define_arm_cp_regs(cpu, zcr_reginfo);
}
#ifdef TARGET_AARCH64
--
2.25.1
- [PULL 00/32] target-arm queue, Peter Maydell, 2022/05/09
- [PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm, Peter Maydell, 2022/05/09
- [PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks, Peter Maydell, 2022/05/09
- [PULL 04/32] target/arm: Merge zcr reginfo,
Peter Maydell <=
- [PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2, Peter Maydell, 2022/05/09
- [PULL 02/32] target/arm: Handle cpreg registration for missing EL, Peter Maydell, 2022/05/09
- [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c, Peter Maydell, 2022/05/09
- [PULL 09/32] target/arm: Split out aa32_max_features, Peter Maydell, 2022/05/09
- [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers, Peter Maydell, 2022/05/09
- [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes, Peter Maydell, 2022/05/09
- [PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max, Peter Maydell, 2022/05/09
- [PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57, Peter Maydell, 2022/05/09
- [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max, Peter Maydell, 2022/05/09
- [PULL 15/32] target/arm: Enable SCR and HCR bits for RAS, Peter Maydell, 2022/05/09