[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests
From: |
Michael S. Tsirkin |
Subject: |
[PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests |
Date: |
Mon, 16 May 2022 06:36:58 -0400 |
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
At this stage we can boot configurations with host bridges,
root ports and type 3 memory devices, so add appropriate
tests.
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20220429144110.25167-23-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
---
tests/qtest/cxl-test.c | 127 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 127 insertions(+)
diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c
index c031049930..5f0794e816 100644
--- a/tests/qtest/cxl-test.c
+++ b/tests/qtest/cxl-test.c
@@ -8,15 +8,142 @@
#include "qemu/osdep.h"
#include "libqtest-single.h"
+#define QEMU_PXB_CMD "-machine q35,cxl=on " \
+ "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 "
+
+#define QEMU_2PXB_CMD "-machine q35,cxl=on " \
+ "-device pxb-cxl,id=cxl.0,bus=pcie.0,bus_nr=52 " \
+ "-device pxb-cxl,id=cxl.1,bus=pcie.0,bus_nr=53 "
+
+#define QEMU_RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 "
+
+/* Dual ports on first pxb */
+#define QEMU_2RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+ "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 "
+
+/* Dual ports on each of the pxb instances */
+#define QEMU_4RP "-device cxl-rp,id=rp0,bus=cxl.0,chassis=0,slot=0 " \
+ "-device cxl-rp,id=rp1,bus=cxl.0,chassis=0,slot=1 " \
+ "-device cxl-rp,id=rp2,bus=cxl.1,chassis=0,slot=2 " \
+ "-device cxl-rp,id=rp3,bus=cxl.1,chassis=0,slot=3 "
+
+#define QEMU_T3D "-object
memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M "
\
+ "-device
cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 "
+
+#define QEMU_2T3D "-object
memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M "
\
+ "-device
cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
+ "-object
memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M "
\
+ "-device
cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 "
+
+#define QEMU_4T3D "-object
memory-backend-file,id=cxl-mem0,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa0,mem-path=%s,size=256M "
\
+ "-device
cxl-type3,bus=rp0,memdev=cxl-mem0,lsa=lsa0,id=cxl-pmem0 " \
+ "-object
memory-backend-file,id=cxl-mem1,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa1,mem-path=%s,size=256M "
\
+ "-device
cxl-type3,bus=rp1,memdev=cxl-mem1,lsa=lsa1,id=cxl-pmem1 " \
+ "-object
memory-backend-file,id=cxl-mem2,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa2,mem-path=%s,size=256M "
\
+ "-device
cxl-type3,bus=rp2,memdev=cxl-mem2,lsa=lsa2,id=cxl-pmem2 " \
+ "-object
memory-backend-file,id=cxl-mem3,mem-path=%s,size=256M " \
+ "-object memory-backend-file,id=lsa3,mem-path=%s,size=256M "
\
+ "-device
cxl-type3,bus=rp3,memdev=cxl-mem3,lsa=lsa3,id=cxl-pmem3 "
+
+static void cxl_basic_hb(void)
+{
+ qtest_start("-machine q35,cxl=on");
+ qtest_end();
+}
+
static void cxl_basic_pxb(void)
{
qtest_start("-machine q35,cxl=on -device pxb-cxl,bus=pcie.0");
qtest_end();
}
+static void cxl_pxb_with_window(void)
+{
+ qtest_start(QEMU_PXB_CMD);
+ qtest_end();
+}
+
+static void cxl_2pxb_with_window(void)
+{
+ qtest_start(QEMU_2PXB_CMD);
+ qtest_end();
+}
+
+static void cxl_root_port(void)
+{
+ qtest_start(QEMU_PXB_CMD QEMU_RP);
+ qtest_end();
+}
+
+static void cxl_2root_port(void)
+{
+ qtest_start(QEMU_PXB_CMD QEMU_2RP);
+ qtest_end();
+}
+
+static void cxl_t3d(void)
+{
+ g_autoptr(GString) cmdline = g_string_new(NULL);
+ char template[] = "/tmp/cxl-test-XXXXXX";
+ const char *tmpfs;
+
+ tmpfs = mkdtemp(template);
+
+ g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs, tmpfs);
+
+ qtest_start(cmdline->str);
+ qtest_end();
+}
+
+static void cxl_1pxb_2rp_2t3d(void)
+{
+ g_autoptr(GString) cmdline = g_string_new(NULL);
+ char template[] = "/tmp/cxl-test-XXXXXX";
+ const char *tmpfs;
+
+ tmpfs = mkdtemp(template);
+
+ g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D,
+ tmpfs, tmpfs, tmpfs, tmpfs);
+
+ qtest_start(cmdline->str);
+ qtest_end();
+}
+
+static void cxl_2pxb_4rp_4t3d(void)
+{
+ g_autoptr(GString) cmdline = g_string_new(NULL);
+ char template[] = "/tmp/cxl-test-XXXXXX";
+ const char *tmpfs;
+
+ tmpfs = mkdtemp(template);
+
+ g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D,
+ tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs,
+ tmpfs, tmpfs);
+
+ qtest_start(cmdline->str);
+ qtest_end();
+}
+
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
+
+ qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb);
qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb);
+ qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window);
+ qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window);
+ qtest_add_func("/pci/cxl/rp", cxl_root_port);
+ qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port);
+ qtest_add_func("/pci/cxl/type3_device", cxl_t3d);
+ qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d);
+ qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4t3d);
return g_test_run();
}
--
MST
- [PULL 14/91] hw/pci/cxl: Create a CXL bus type, (continued)
- [PULL 14/91] hw/pci/cxl: Create a CXL bus type, Michael S. Tsirkin, 2022/05/16
- [PULL 15/91] cxl: Machine level control on whether CXL support is enabled, Michael S. Tsirkin, 2022/05/16
- [PULL 17/91] qtest/cxl: Introduce initial test for pxb-cxl only., Michael S. Tsirkin, 2022/05/16
- [PULL 16/91] hw/pxb: Allow creation of a CXL PXB (host bridge), Michael S. Tsirkin, 2022/05/16
- [PULL 18/91] hw/cxl/rp: Add a root port, Michael S. Tsirkin, 2022/05/16
- [PULL 19/91] hw/cxl/device: Add a memory device (8.2.8.5), Michael S. Tsirkin, 2022/05/16
- [PULL 20/91] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12), Michael S. Tsirkin, 2022/05/16
- [PULL 21/91] hw/cxl/device: Add some trivial commands, Michael S. Tsirkin, 2022/05/16
- [PULL 22/91] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing, Michael S. Tsirkin, 2022/05/16
- [PULL 23/91] hw/cxl/device: Implement get/set Label Storage Area (LSA), Michael S. Tsirkin, 2022/05/16
- [PULL 24/91] qtests/cxl: Add initial root port and CXL type3 tests,
Michael S. Tsirkin <=
- [PULL 25/91] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142), Michael S. Tsirkin, 2022/05/16
- [PULL 26/91] acpi/cxl: Add _OSC implementation (9.14.2), Michael S. Tsirkin, 2022/05/16
- [PULL 27/91] acpi/cxl: Create the CEDT (9.14.1), Michael S. Tsirkin, 2022/05/16
- [PULL 28/91] hw/cxl/component: Add utils for interleave parameter encoding/decoding, Michael S. Tsirkin, 2022/05/16
- [PULL 29/91] hw/cxl/host: Add support for CXL Fixed Memory Windows., Michael S. Tsirkin, 2022/05/16
- [PULL 30/91] acpi/cxl: Introduce CFMWS structures in CEDT, Michael S. Tsirkin, 2022/05/16
- [PULL 31/91] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl, Michael S. Tsirkin, 2022/05/16
- [PULL 32/91] pci/pcie_port: Add pci_find_port_by_pn(), Michael S. Tsirkin, 2022/05/16
- [PULL 33/91] CXL/cxl_component: Add cxl_get_hb_cstate(), Michael S. Tsirkin, 2022/05/16
- [PULL 35/91] cxl/cxl-host: Add memops for CFMWS region., Michael S. Tsirkin, 2022/05/16