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[PATCH v5 24/43] target/loongarch: Add constant timer support
From: |
Xiaojuan Yang |
Subject: |
[PATCH v5 24/43] target/loongarch: Add constant timer support |
Date: |
Tue, 24 May 2022 16:17:45 +0800 |
Signed-off-by: Xiaojuan Yang <yangxiaojuan@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/loongarch/constant_timer.c | 64 +++++++++++++++++++++++++++++++
target/loongarch/cpu.c | 2 +
target/loongarch/cpu.h | 4 ++
target/loongarch/internals.h | 6 +++
target/loongarch/meson.build | 1 +
5 files changed, 77 insertions(+)
create mode 100644 target/loongarch/constant_timer.c
diff --git a/target/loongarch/constant_timer.c
b/target/loongarch/constant_timer.c
new file mode 100644
index 0000000000..1851f53fd6
--- /dev/null
+++ b/target/loongarch/constant_timer.c
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * QEMU LoongArch constant timer support
+ *
+ * Copyright (c) 2021 Loongson Technology Corporation Limited
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/timer.h"
+#include "cpu.h"
+#include "internals.h"
+#include "cpu-csr.h"
+
+#define TIMER_PERIOD 10 /* 10 ns period for 100 MHz frequency */
+#define CONSTANT_TIMER_TICK_MASK 0xfffffffffffcUL
+#define CONSTANT_TIMER_ENABLE 0x1UL
+
+uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu)
+{
+ return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / TIMER_PERIOD;
+}
+
+uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu)
+{
+ uint64_t now, expire;
+
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ expire = timer_expire_time_ns(&cpu->timer);
+
+ return (expire - now) / TIMER_PERIOD;
+}
+
+void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
+ uint64_t value)
+{
+ CPULoongArchState *env = &cpu->env;
+ uint64_t now, next;
+
+ env->CSR_TCFG = value;
+ if (value & CONSTANT_TIMER_ENABLE) {
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ next = now + (value & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
+ timer_mod(&cpu->timer, next);
+ } else {
+ timer_del(&cpu->timer);
+ }
+}
+
+void loongarch_constant_timer_cb(void *opaque)
+{
+ LoongArchCPU *cpu = opaque;
+ CPULoongArchState *env = &cpu->env;
+ uint64_t now, next;
+
+ if (FIELD_EX64(env->CSR_TCFG, CSR_TCFG, PERIODIC)) {
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
+ next = now + (env->CSR_TCFG & CONSTANT_TIMER_TICK_MASK) * TIMER_PERIOD;
+ timer_mod(&cpu->timer, next);
+ } else {
+ env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
+ }
+
+ loongarch_cpu_set_irq(opaque, IRQ_TIMER, 1);
+}
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 480688b039..686a9d16b3 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -490,6 +490,8 @@ static void loongarch_cpu_init(Object *obj)
cpu_set_cpustate_pointers(cpu);
qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
+ timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
+ &loongarch_constant_timer_cb, cpu);
}
static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index b983ce241c..2081902f2e 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -11,6 +11,7 @@
#include "exec/cpu-defs.h"
#include "fpu/softfloat-types.h"
#include "hw/registerfields.h"
+#include "qemu/timer.h"
#define TCG_GUEST_DEFAULT_MO (0)
@@ -185,6 +186,8 @@ extern const char * const regnames[32];
extern const char * const fregnames[32];
#define N_IRQS 13
+#define IRQ_TIMER 11
+#define IRQ_IPI 12
#define LOONGARCH_STLB 2048 /* 2048 STLB */
#define LOONGARCH_MTLB 64 /* 64 MTLB */
@@ -295,6 +298,7 @@ struct ArchCPU {
CPUNegativeOffsetState neg;
CPULoongArchState env;
+ QEMUTimer timer;
};
#define TYPE_LOONGARCH_CPU "loongarch-cpu"
diff --git a/target/loongarch/internals.h b/target/loongarch/internals.h
index 69183e8bb5..4b1bcd7c0f 100644
--- a/target/loongarch/internals.h
+++ b/target/loongarch/internals.h
@@ -32,6 +32,12 @@ extern const VMStateDescription vmstate_loongarch_cpu;
void loongarch_cpu_set_irq(void *opaque, int irq, int level);
+void loongarch_constant_timer_cb(void *opaque);
+uint64_t cpu_loongarch_get_constant_timer_counter(LoongArchCPU *cpu);
+uint64_t cpu_loongarch_get_constant_timer_ticks(LoongArchCPU *cpu);
+void cpu_loongarch_store_constant_timer_config(LoongArchCPU *cpu,
+ uint64_t value);
+
bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
diff --git a/target/loongarch/meson.build b/target/loongarch/meson.build
index 435cc75999..04e15ba1e3 100644
--- a/target/loongarch/meson.build
+++ b/target/loongarch/meson.build
@@ -18,6 +18,7 @@ loongarch_softmmu_ss = ss.source_set()
loongarch_softmmu_ss.add(files(
'machine.c',
'tlb_helper.c',
+ 'constant_timer.c',
))
loongarch_ss.add_all(when: 'CONFIG_TCG', if_true: [loongarch_tcg_ss])
--
2.31.1
- [PATCH v5 01/43] target/loongarch: Add README, (continued)
- [PATCH v5 01/43] target/loongarch: Add README, Xiaojuan Yang, 2022/05/24
- [PATCH v5 10/43] target/loongarch: Add floating point arithmetic instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 08/43] target/loongarch: Add fixed point atomic instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 12/43] target/loongarch: Add floating point conversion instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 11/43] target/loongarch: Add floating point comparison instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 05/43] target/loongarch: Add fixed point shift instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 19/43] target/loongarch: Add CSRs definition, Xiaojuan Yang, 2022/05/24
- [PATCH v5 13/43] target/loongarch: Add floating point move instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 15/43] target/loongarch: Add branch instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 21/43] target/loongarch: Implement qmp_query_cpu_definitions(), Xiaojuan Yang, 2022/05/24
- [PATCH v5 24/43] target/loongarch: Add constant timer support,
Xiaojuan Yang <=
- [PATCH v5 20/43] target/loongarch: Add basic vmstate description of CPU., Xiaojuan Yang, 2022/05/24
- [PATCH v5 14/43] target/loongarch: Add floating point load/store instruction translation, Xiaojuan Yang, 2022/05/24
- [PATCH v5 02/43] target/loongarch: Add core definition, Xiaojuan Yang, 2022/05/24
- [PATCH v5 22/43] target/loongarch: Add MMU support for LoongArch CPU., Xiaojuan Yang, 2022/05/24
- [PATCH v5 37/43] hw/loongarch: Add some devices support for 3A5000., Xiaojuan Yang, 2022/05/24
- [PATCH v5 03/43] target/loongarch: Add main translation routines, Xiaojuan Yang, 2022/05/24
- [PATCH v5 27/43] target/loongarch: Add TLB instruction support, Xiaojuan Yang, 2022/05/24
- [PATCH v5 28/43] target/loongarch: Add other core instructions support, Xiaojuan Yang, 2022/05/24
- [PATCH v5 40/43] hw/loongarch: Add LoongArch ls7a acpi device support, Xiaojuan Yang, 2022/05/24