[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 05/23] target/riscv: Add short-isa-string option
From: |
Alistair Francis |
Subject: |
[PULL 05/23] target/riscv: Add short-isa-string option |
Date: |
Wed, 25 May 2022 08:44:10 +1000 |
From: Tsukasa OI <research_trasio@irq.a4lg.com>
Because some operating systems don't correctly parse long ISA extension
string, this commit adds short-isa-string boolean option to disable
generating long ISA extension strings on Device Tree.
For instance, enabling Zfinx and Zdinx extensions and booting Linux (5.17 or
earlier) with FPU support caused a kernel panic.
Operating Systems which short-isa-string might be helpful:
1. Linux (5.17 or earlier)
2. FreeBSD (at least 14.0-CURRENT)
3. OpenBSD (at least current development version)
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id:
<7c1fe5f06b0a7646a47e9bcdddb1042bb60c69c8.1652181972.git.research_trasio@irq.a4lg.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 2 ++
target/riscv/cpu.c | 6 +++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fe6c9a2c92..f5ff7294c6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -425,6 +425,8 @@ struct RISCVCPUConfig {
bool aia;
bool debug;
uint64_t resetvec;
+
+ bool short_isa_string;
};
typedef struct RISCVCPUConfig RISCVCPUConfig;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 9f38e56316..dc93412395 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -879,6 +879,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false),
DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC),
+
+ DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string,
false),
DEFINE_PROP_END_OF_LIST(),
};
@@ -1049,7 +1051,9 @@ char *riscv_isa_string(RISCVCPU *cpu)
}
}
*p = '\0';
- riscv_isa_string_ext(cpu, &isa_str, maxlen);
+ if (!cpu->cfg.short_isa_string) {
+ riscv_isa_string_ext(cpu, &isa_str, maxlen);
+ }
return isa_str;
}
--
2.35.3
- [PULL 00/23] riscv-to-apply queue, Alistair Francis, 2022/05/24
- [PULL 01/23] target/riscv: Fix VS mode hypervisor CSR access, Alistair Francis, 2022/05/24
- [PULL 02/23] target/riscv: rvv: Fix early exit condition for whole register load/store, Alistair Francis, 2022/05/24
- [PULL 03/23] hw/intc: Pass correct hartid while updating mtimecmp, Alistair Francis, 2022/05/24
- [PULL 04/23] target/riscv: Move Zhinx* extensions on ISA string, Alistair Francis, 2022/05/24
- [PULL 05/23] target/riscv: Add short-isa-string option,
Alistair Francis <=
- [PULL 06/23] hw/riscv: Make CPU config error handling generous (virt/spike), Alistair Francis, 2022/05/24
- [PULL 07/23] hw/riscv: Make CPU config error handling generous (sifive_e/u/opentitan), Alistair Francis, 2022/05/24
- [PULL 08/23] target/riscv: Fix coding style on "G" expansion, Alistair Francis, 2022/05/24
- [PULL 09/23] target/riscv: Disable "G" by default, Alistair Francis, 2022/05/24
- [PULL 10/23] target/riscv: Change "G" expansion, Alistair Francis, 2022/05/24
- [PULL 13/23] hw/vfio/pci-quirks: Resolve redundant property getters, Alistair Francis, 2022/05/24
- [PULL 12/23] target/riscv: Move/refactor ISA extension checks, Alistair Francis, 2022/05/24
- [PULL 14/23] hw/riscv/sifive_u: Resolve redundant property accessors, Alistair Francis, 2022/05/24
- [PULL 15/23] target/riscv: check 'I' and 'E' after checking 'G' in riscv_cpu_realize, Alistair Francis, 2022/05/24
- [PULL 16/23] target/riscv: Fix typo of mimpid cpu option, Alistair Francis, 2022/05/24