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[PULL 07/25] target/riscv/debug.c: keep experimental rv128 support worki
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From: |
Alistair Francis |
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Subject: |
[PULL 07/25] target/riscv/debug.c: keep experimental rv128 support working |
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Date: |
Fri, 10 Jun 2022 14:26:37 +1000 |
From: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Add an MXL_RV128 case in two switches so that no error is triggered when
using the -cpu x-rv128 option.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220602155246.38837-1-frederic.petrot@univ-grenoble-alpes.fr>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/debug.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 2f2a51c732..fc6e13222f 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -77,6 +77,7 @@ static inline target_ulong trigger_type(CPURISCVState *env,
tdata1 = RV32_TYPE(type);
break;
case MXL_RV64:
+ case MXL_RV128:
tdata1 = RV64_TYPE(type);
break;
default:
@@ -123,6 +124,7 @@ static target_ulong tdata1_validate(CPURISCVState *env,
target_ulong val,
tdata1 = RV32_TYPE(t);
break;
case MXL_RV64:
+ case MXL_RV128:
type = extract64(val, 60, 4);
dmode = extract64(val, 59, 1);
tdata1 = RV64_TYPE(t);
--
2.36.1
- [PULL 00/25] riscv-to-apply queue, Alistair Francis, 2022/06/10
- [PULL 01/25] MAINTAINERS: Cover hw/core/uboot_image.h within Generic Loader section, Alistair Francis, 2022/06/10
- [PULL 02/25] target/riscv: add support for zmmul extension v0.1, Alistair Francis, 2022/06/10
- [PULL 03/25] hw/riscv: virt: Generate fw_cfg DT node correctly, Alistair Francis, 2022/06/10
- [PULL 04/25] hw/intc: sifive_plic: Avoid overflowing the addr_config buffer, Alistair Francis, 2022/06/10
- [PULL 05/25] hw/core/loader: return image sizes as ssize_t, Alistair Francis, 2022/06/10
- [PULL 06/25] target/riscv: Wake on VS-level external interrupts, Alistair Francis, 2022/06/10
- [PULL 07/25] target/riscv/debug.c: keep experimental rv128 support working,
Alistair Francis <=
- [PULL 08/25] target/riscv: rvv: Prune redundant ESZ, DSZ parameter passed, Alistair Francis, 2022/06/10
- [PULL 11/25] target/riscv: rvv: Early exit when vstart >= vl, Alistair Francis, 2022/06/10
- [PULL 09/25] target/riscv: rvv: Prune redundant access_type parameter passed, Alistair Francis, 2022/06/10
- [PULL 13/25] target/riscv: rvv: Add tail agnostic for vector load / store instructions, Alistair Francis, 2022/06/10
- [PULL 12/25] target/riscv: rvv: Add tail agnostic for vv instructions, Alistair Francis, 2022/06/10
- [PULL 17/25] target/riscv: rvv: Add tail agnostic for vector integer merge and move instructions, Alistair Francis, 2022/06/10
- [PULL 10/25] target/riscv: rvv: Rename ambiguous esz, Alistair Francis, 2022/06/10
- [PULL 16/25] target/riscv: rvv: Add tail agnostic for vector integer comparison instructions, Alistair Francis, 2022/06/10
- [PULL 14/25] target/riscv: rvv: Add tail agnostic for vx, vvm, vxm instructions, Alistair Francis, 2022/06/10
- [PULL 15/25] target/riscv: rvv: Add tail agnostic for vector integer shift instructions, Alistair Francis, 2022/06/10