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[PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11
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From: |
Alistair Francis |
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Subject: |
[PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11 |
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Date: |
Sun, 3 Jul 2022 10:12:29 +1000 |
From: Alistair Francis <alistair.francis@wdc.com>
The Ibex CPU supports version 1.11 of the priv spec [1], so let's
correct that in QEMU as well.
1: https://ibex-core.readthedocs.io/en/latest/01_overview/compliance.html
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220629233102.275181-3-alistair.francis@opensource.wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index d12c6dc630..aac0576fe1 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -237,7 +237,7 @@ static void rv32_ibex_cpu_init(Object *obj)
RISCVCPU *cpu = RISCV_CPU(obj);
set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
- set_priv_version(env, PRIV_VERSION_1_10_0);
+ set_priv_version(env, PRIV_VERSION_1_11_0);
cpu->cfg.mmu = false;
cpu->cfg.epmp = true;
}
--
2.36.1
- [PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size, (continued)
- [PULL v2 05/19] target/riscv/pmp: guard against PMP ranges with a negative size, Alistair Francis, 2022/07/02
- [PULL v2 06/19] target/riscv: Fix PMU CSR predicate function, Alistair Francis, 2022/07/02
- [PULL v2 07/19] target/riscv: Implement PMU CSR predicate function for S-mode, Alistair Francis, 2022/07/02
- [PULL v2 08/19] target/riscv: pmu: Rename the counters extension to pmu, Alistair Francis, 2022/07/02
- [PULL v2 04/19] target/riscv: Minimize the calls to decode_save_opc, Alistair Francis, 2022/07/02
- [PULL v2 09/19] target/riscv: pmu: Make number of counters configurable, Alistair Francis, 2022/07/02
- [PULL v2 10/19] target/riscv: Implement mcountinhibit CSR, Alistair Francis, 2022/07/02
- [PULL v2 11/19] target/riscv: Add support for hpmcounters/hpmevents, Alistair Francis, 2022/07/02
- [PULL v2 12/19] target/riscv: Support mcycle/minstret write operation, Alistair Francis, 2022/07/02
- [PULL v2 13/19] target/riscv: Fixup MSECCFG minimum priv check, Alistair Francis, 2022/07/02
- [PULL v2 14/19] target/riscv: Ibex: Support priv version 1.11,
Alistair Francis <=
- [PULL v2 15/19] target/riscv: Don't force update priv spec version to latest, Alistair Francis, 2022/07/02
- [PULL v2 16/19] hw/riscv: boot: Reduce FDT address alignment constraints, Alistair Francis, 2022/07/02
- [PULL v2 17/19] target/riscv: Set minumum priv spec version for mcountinhibit, Alistair Francis, 2022/07/02
- [PULL v2 18/19] target/riscv: Remove CSRs that set/clear an IMSIC interrupt file bits, Alistair Francis, 2022/07/02
- [PULL v2 19/19] target/riscv: Update default priority table for local interrupts, Alistair Francis, 2022/07/02
- Re: [PULL v2 00/19] riscv-to-apply queue, Richard Henderson, 2022/07/03