[PATCH v11 12/15] target/hexagon: prepare frontend for parser

[Anton Johansson]

This patch adds the necessary changes to the Hexagon frontend, required
by idef-parser to deal with a :mem_noshuf packet with a store in slot 1
and predicated load in slot 0.

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/hexagon/cpu.h       |  8 ++++++++
 target/hexagon/translate.c | 22 ++++++++++++++++++++++
 target/hexagon/translate.h |  2 ++
 3 files changed, 32 insertions(+)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 2a65a57bab..1511e5a73e 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -107,6 +107,14 @@ typedef struct CPUArchState {
     target_ulong llsc_val;
     uint64_t     llsc_val_i64;
 
+    /*
+     * Global state which keeps tracks of whether or not a process_store was
+     * actually executed at runtime. Used only for :mem_noshuf packets with a
+     * pload instruction to execute the process_store at packet commit if the
+     * predicated branch is not taken.
+     */
+    target_ulong did_s1_store;
+
     MMVector VRegs[NUM_VREGS] QEMU_ALIGNED(16);
     MMVector future_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
     MMVector tmp_VRegs[VECTOR_TEMPS_MAX] QEMU_ALIGNED(16);
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index e3e250fd4f..72bf8d591b 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -53,6 +53,7 @@ TCGv hex_QRegs_updated;
 TCGv hex_vstore_addr[VSTORES_MAX];
 TCGv hex_vstore_size[VSTORES_MAX];
 TCGv hex_vstore_pending[VSTORES_MAX];
+TCGv hex_did_s1_store;
 
 static const char * const hexagon_prednames[] = {
   "p0", "p1", "p2", "p3"
@@ -239,6 +240,9 @@ static void gen_start_packet(DisasContext *ctx, Packet *pkt)
         tcg_gen_movi_tl(hex_this_PC, ctx->base.pc_next);
     }
 
+    ctx->insn_is_noshuf_pload = false;
+    tcg_gen_movi_tl(hex_did_s1_store, 0);
+
     /* Initialize the runtime state for packet semantics */
     if (need_pc(pkt)) {
         tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next);
@@ -494,6 +498,22 @@ void process_store(DisasContext *ctx, Packet *pkt, int 
slot_num)
 
 static void process_store_log(DisasContext *ctx, Packet *pkt)
 {
+    /*
+     * Here we deal with the special case of a :mem_noshuf packet with a
+     * predicated load in slot 0 with a store in slot 1. If the predicated
+     * branch wasn't taken during packet execution, then store in slot 1
+     * will not have been executed, corresponding to hex_did_store_s1 being 0.
+     * If this is the case, process the store here.
+     */
+    if (ctx->insn_is_noshuf_pload) {
+        TCGLabel *l = gen_new_label();
+        /* Reset s1_store_processed so process_store actually emits a store */
+        ctx->s1_store_processed = false;
+        tcg_gen_brcondi_tl(TCG_COND_EQ, hex_did_s1_store, 1, l);
+        process_store(ctx, pkt, 1);
+        gen_set_label(l);
+    }
+
     /*
      *  When a packet has two stores, the hardware processes
      *  slot 1 and then slot 0.  This will be important when
@@ -925,6 +945,8 @@ void hexagon_translate_init(void)
         offsetof(CPUHexagonState, llsc_val), "llsc_val");
     hex_llsc_val_i64 = tcg_global_mem_new_i64(cpu_env,
         offsetof(CPUHexagonState, llsc_val_i64), "llsc_val_i64");
+    hex_did_s1_store = tcg_global_mem_new(cpu_env,
+        offsetof(CPUHexagonState, did_s1_store), "did_s1_store");
     hex_VRegs_updated = tcg_global_mem_new(cpu_env,
         offsetof(CPUHexagonState, VRegs_updated), "VRegs_updated");
     hex_QRegs_updated = tcg_global_mem_new(cpu_env,
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index 494471548e..f340ed8fb6 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -54,6 +54,7 @@ typedef struct DisasContext {
     int qreg_log_idx;
     bool pre_commit;
     uint32_t npc;
+    bool insn_is_noshuf_pload;
 } DisasContext;
 
 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum)
@@ -147,6 +148,7 @@ extern TCGv hex_QRegs_updated;
 extern TCGv hex_vstore_addr[VSTORES_MAX];
 extern TCGv hex_vstore_size[VSTORES_MAX];
 extern TCGv hex_vstore_pending[VSTORES_MAX];
+extern TCGv hex_did_s1_store;
 
 bool is_gather_store_insn(Insn *insn, Packet *pkt);
 void process_store(DisasContext *ctx, Packet *pkt, int slot_num);
-- 
2.37.0