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[PATCH v2 04/37] target/i386: introduce insn_get_addr
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From: |
Paolo Bonzini |
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Subject: |
[PATCH v2 04/37] target/i386: introduce insn_get_addr |
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Date: |
Tue, 20 Sep 2022 19:24:34 +0200 |
The "O" operand type in the Intel SDM needs to load an 8- to 64-bit
unsigned value, while insn_get is limited to 32 bits. Extract the code
out of disas_insn and into a separate function.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
target/i386/tcg/translate.c | 36 ++++++++++++++++++++++++++----------
1 file changed, 26 insertions(+), 10 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 0f45a9f5ad..9d0e128a6a 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -2308,6 +2308,31 @@ static void gen_ldst_modrm(CPUX86State *env,
DisasContext *s, int modrm,
}
}
+static target_ulong insn_get_addr(CPUX86State *env, DisasContext *s, MemOp ot)
+{
+ target_ulong ret;
+
+ switch (ot) {
+ case MO_8:
+ ret = x86_ldub_code(env, s);
+ break;
+ case MO_16:
+ ret = x86_lduw_code(env, s);
+ break;
+ case MO_32:
+ ret = x86_ldl_code(env, s);
+ break;
+#ifdef TARGET_X86_64
+ case MO_64:
+ ret = x86_ldq_code(env, s);
+ break;
+#endif
+ default:
+ g_assert_not_reached();
+ }
+ return ret;
+}
+
static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, MemOp ot)
{
uint32_t ret;
@@ -5882,16 +5907,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState
*cpu)
target_ulong offset_addr;
ot = mo_b_d(b, dflag);
- switch (s->aflag) {
-#ifdef TARGET_X86_64
- case MO_64:
- offset_addr = x86_ldq_code(env, s);
- break;
-#endif
- default:
- offset_addr = insn_get(env, s, s->aflag);
- break;
- }
+ offset_addr = insn_get_addr(env, s, s->aflag);
tcg_gen_movi_tl(s->A0, offset_addr);
gen_add_A0_ds_seg(s);
if ((b & 2) == 0) {
--
2.37.2
- Re: [PATCH v2 06/37] target/i386: add ALU load/writeback core, (continued)
- [PATCH v2 25/37] target/i386: clarify (un)signedness of immediates from 0F3Ah opcodes, Paolo Bonzini, 2022/09/20
- [PATCH v2 02/37] target/i386: make ldo/sto operations consistent with ldq, Paolo Bonzini, 2022/09/20
- [PATCH v2 08/37] target/i386: add CPUID feature checks to new decoder, Paolo Bonzini, 2022/09/20
- [PATCH v2 22/37] target/i386: reimplement 0x0f 0x78-0x7f, add AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 19/37] target/i386: reimplement 0x0f 0x60-0x6f, add AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 04/37] target/i386: introduce insn_get_addr,
Paolo Bonzini <=
- [PATCH v2 03/37] target/i386: REPZ and REPNZ are mutually exclusive, Paolo Bonzini, 2022/09/20
- [PATCH v2 16/37] target/i386: provide 3-operand versions of unary scalar helpers, Paolo Bonzini, 2022/09/20
- [PATCH v2 13/37] target/i386: Prepare ops_sse_header.h for 256 bit AVX, Paolo Bonzini, 2022/09/20
- [PATCH v2 12/37] target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder, Paolo Bonzini, 2022/09/20
- [PATCH v2 10/37] target/i386: validate VEX prefixes via the instructions' exception classes, Paolo Bonzini, 2022/09/20
- [PATCH v2 09/37] target/i386: add AVX_EN hflag, Paolo Bonzini, 2022/09/20
- [PATCH v2 14/37] target/i386: extend helpers to support VEX.V 3- and 4- operand encodings, Paolo Bonzini, 2022/09/20
- [PATCH v2 27/37] target/i386: Use tcg gvec ops for pmovmskb, Paolo Bonzini, 2022/09/20