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Re: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking
From: |
Peter Maydell |
Subject: |
Re: [PATCH v3 27/42] target/arm: Use softmmu tlbs for page table walking |
Date: |
Fri, 7 Oct 2022 17:08:39 +0100 |
On Fri, 7 Oct 2022 at 16:27, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> On 10/7/22 02:01, Peter Maydell wrote:
> > The upcoming v8R support has its stage 2 attributes in the MAIR
> > format, so it might be a little awkward to assume the v8A-stage-2
> > format here rather than being able to add the "if !is_s2_format"
> > condition. I guess we'll deal with that when we get to it...
>
> Ah. I had wondered whether it would be better to convert the result here, so
> that we
> always have the MAIR format. I decided against it within the scope of this
> patch set
> because it meant that I kept the existing s1+s2 attribute merging logic
> unchanged.
Unfortunately, for A-profile you can't just convert the s2 attrs
to MAIR format, because their interpretation depends on the
s1 attr values in the FWB case. So you have to keep the s2
attrs as raw until they get to the point of combination.
(v8R doesn't have any equivalent of FWB.)
thanks
-- PMM
- [PATCH v3 24/42] target/arm: Add ARMMMUIdx_Phys_{S,NS}, (continued)
- [PATCH v3 28/42] target/arm: Split out get_phys_addr_twostage, Richard Henderson, 2022/10/01
- [PATCH v3 29/42] target/arm: Use bool consistently for get_phys_addr subroutines, Richard Henderson, 2022/10/01
- [PATCH v3 30/42] target/arm: Add ptw_idx argument to S1_ptw_translate, Richard Henderson, 2022/10/01
- [PATCH v3 31/42] target/arm: Add isar predicates for FEAT_HAFDBS, Richard Henderson, 2022/10/01
- [PATCH v3 32/42] target/arm: Extract HA and HD in aa64_va_parameters, Richard Henderson, 2022/10/01