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From: | Richard Henderson |
Subject: | Re: [PATCH] include/qemu/atomic128: Support 16-byte atomic read/write for Intel AVX |
Date: | Sat, 8 Oct 2022 08:43:54 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.11.0 |
On 10/8/22 08:36, Richard Henderson wrote:
Intel has now given guarantees about the atomicity of SSE read and write instructions on cpus supporting AVX. We can use these instead of the much slower cmpxchg16b. Derived from https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- Paolo, we probably ought to modify gen_ld[oy]_env_A0 to match, at least with CF_PARALLEL set.
Or, rather, just gen_ldo/sto. Curiously, there are no guarantees at all for vmovdqa mem, %ymmN r~
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