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[PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae
From: |
Peter Maydell |
Subject: |
[PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae |
Date: |
Mon, 10 Oct 2022 15:27:08 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Remove the use of regime_is_secure from get_phys_addr_lpae,
using the new parameter instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20221001162318.153420-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 7d763a58477..96ed8e13afc 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -16,8 +16,8 @@
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool s1_is_el0, GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+ bool is_secure, bool s1_is_el0,
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
@@ -207,8 +207,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx
mmu_idx,
GetPhysAddrResult s2 = {};
int ret;
- ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
- &s2, fi);
+ ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
+ *is_secure, false, &s2, fi);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
@@ -965,8 +965,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64,
int level,
*/
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool s1_is_el0, GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+ bool is_secure, bool s1_is_el0,
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
/* Read an LPAE long-descriptor translation table. */
@@ -1183,7 +1183,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
* remain non-secure. We implement this by just ORing in the NSTable/NS
* bits at each step.
*/
- tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
+ tableattrs = is_secure ? 0 : (1 << 4);
for (;;) {
uint64_t descriptor;
bool nstable;
@@ -2337,7 +2337,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
memset(result, 0, sizeof(*result));
ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
- is_el0, result, fi);
+ s2walk_secure, is_el0, result, fi);
fi->s2addr = ipa;
/* Combine the S1 and S2 perms. */
@@ -2504,8 +2504,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
}
if (regime_using_lpae_format(env, mmu_idx)) {
- return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
- result, fi);
+ return get_phys_addr_lpae(env, address, access_type, mmu_idx,
+ is_secure, false, result, fi);
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx,
is_secure, result, fi);
--
2.25.1
- [PULL 00/28] target-arm queue, Peter Maydell, 2022/10/10
- [PULL 02/28] target/arm: allow setting SCR_EL3.EnTP2 when FEAT_SME is implemented, Peter Maydell, 2022/10/10
- [PULL 01/28] target/arm/kvm: Retry KVM_CREATE_VM call if it fails EINTR, Peter Maydell, 2022/10/10
- [PULL 03/28] docs/nuvoton: Update URL for images, Peter Maydell, 2022/10/10
- [PULL 04/28] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/10
- [PULL 05/28] target/arm: Make the final stage1+2 write to secure be unconditional, Peter Maydell, 2022/10/10
- [PULL 06/28] target/arm: Add is_secure parameter to get_phys_addr_lpae,
Peter Maydell <=
- [PULL 07/28] target/arm: Fix S2 disabled check in S1_ptw_translate, Peter Maydell, 2022/10/10
- [PULL 08/28] target/arm: Add is_secure parameter to regime_translation_disabled, Peter Maydell, 2022/10/10
- [PULL 09/28] target/arm: Split out get_phys_addr_with_secure, Peter Maydell, 2022/10/10
- [PULL 10/28] target/arm: Add is_secure parameter to v7m_read_half_insn, Peter Maydell, 2022/10/10
- [PULL 11/28] target/arm: Add TBFLAG_M32.SECURE, Peter Maydell, 2022/10/10
- [PULL 16/28] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Peter Maydell, 2022/10/10
- [PULL 23/28] target/arm: Fix cacheattr in get_phys_addr_disabled, Peter Maydell, 2022/10/10
- [PULL 12/28] target/arm: Merge regime_is_secure into get_phys_addr, Peter Maydell, 2022/10/10
- [PULL 13/28] target/arm: Add is_secure parameter to do_ats_write, Peter Maydell, 2022/10/10
- [PULL 14/28] target/arm: Fold secure and non-secure a-profile mmu indexes, Peter Maydell, 2022/10/10