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[PULL 15/30] target/arm: Don't shift attrs in get_phys_addr_lpae
From: |
Peter Maydell |
Subject: |
[PULL 15/30] target/arm: Don't shift attrs in get_phys_addr_lpae |
Date: |
Tue, 25 Oct 2022 17:39:37 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
Leave the upper and lower attributes in the place they originate
from in the descriptor. Shifting them around is confusing, since
one cannot read the bit numbers out of the manual. Also, new
attributes have been added which would alter the shifts.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-id: 20221024051851.3074715-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/ptw.c | 31 +++++++++++++++----------------
1 file changed, 15 insertions(+), 16 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 3302376e42e..691110f70c0 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -1050,7 +1050,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
hwaddr descaddr, indexmask, indexmask_grainsize;
uint32_t tableattrs;
target_ulong page_size;
- uint32_t attrs;
+ uint64_t attrs;
int32_t stride;
int addrsize, inputsize, outputsize;
uint64_t tcr = regime_tcr(env, mmu_idx);
@@ -1324,49 +1324,48 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
descaddr &= ~(hwaddr)(page_size - 1);
descaddr |= (address & (page_size - 1));
/* Extract attributes from the descriptor */
- attrs = extract64(descriptor, 2, 10)
- | (extract64(descriptor, 52, 12) << 10);
+ attrs = descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(52, 12));
if (regime_is_stage2(mmu_idx)) {
/* Stage 2 table descriptors do not include any attribute fields */
goto skip_attrs;
}
/* Merge in attributes from table descriptors */
- attrs |= nstable << 3; /* NS */
+ attrs |= nstable << 5; /* NS */
guarded = extract64(descriptor, 50, 1); /* GP */
if (param.hpd) {
/* HPD disables all the table attributes except NSTable. */
goto skip_attrs;
}
- attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
+ attrs |= extract64(tableattrs, 0, 2) << 53; /* XN, PXN */
/*
* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
* means "force PL1 access only", which means forcing AP[1] to 0.
*/
- attrs &= ~(extract32(tableattrs, 2, 1) << 4); /* !APT[0] => AP[1] */
- attrs |= extract32(tableattrs, 3, 1) << 5; /* APT[1] => AP[2] */
+ attrs &= ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] => AP[1] */
+ attrs |= extract32(tableattrs, 3, 1) << 7; /* APT[1] => AP[2] */
skip_attrs:
/*
* Here descaddr is the final physical address, and attributes
* are all in attrs.
*/
- if ((attrs & (1 << 8)) == 0) {
+ if ((attrs & (1 << 10)) == 0) {
/* Access flag */
fi->type = ARMFault_AccessFlag;
goto do_fault;
}
- ap = extract32(attrs, 4, 2);
+ ap = extract32(attrs, 6, 2);
if (regime_is_stage2(mmu_idx)) {
ns = mmu_idx == ARMMMUIdx_Stage2;
- xn = extract32(attrs, 11, 2);
+ xn = extract64(attrs, 53, 2);
result->f.prot = get_S2prot(env, ap, xn, s1_is_el0);
} else {
- ns = extract32(attrs, 3, 1);
- xn = extract32(attrs, 12, 1);
- pxn = extract32(attrs, 11, 1);
+ ns = extract32(attrs, 5, 1);
+ xn = extract64(attrs, 54, 1);
+ pxn = extract64(attrs, 53, 1);
result->f.prot = get_S1prot(env, mmu_idx, aarch64, ap, ns, xn, pxn);
}
@@ -1391,10 +1390,10 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
if (regime_is_stage2(mmu_idx)) {
result->cacheattrs.is_s2_format = true;
- result->cacheattrs.attrs = extract32(attrs, 0, 4);
+ result->cacheattrs.attrs = extract32(attrs, 2, 4);
} else {
/* Index into MAIR registers for cache attributes */
- uint8_t attrindx = extract32(attrs, 0, 3);
+ uint8_t attrindx = extract32(attrs, 2, 3);
uint64_t mair = env->cp15.mair_el[regime_el(env, mmu_idx)];
assert(attrindx <= 7);
result->cacheattrs.is_s2_format = false;
@@ -1409,7 +1408,7 @@ static bool get_phys_addr_lpae(CPUARMState *env,
S1Translate *ptw,
if (param.ds) {
result->cacheattrs.shareability = param.sh;
} else {
- result->cacheattrs.shareability = extract32(attrs, 6, 2);
+ result->cacheattrs.shareability = extract32(attrs, 8, 2);
}
result->f.phys_addr = descaddr;
--
2.25.1
- [PULL 01/30] target/arm: Implement FEAT_E0PD, (continued)
- [PULL 01/30] target/arm: Implement FEAT_E0PD, Peter Maydell, 2022/10/25
- [PULL 05/30] hw/hyperv/hyperv.c: Use device_cold_reset() instead of device_legacy_reset(), Peter Maydell, 2022/10/25
- [PULL 02/30] hw/arm/virt: Fix devicetree warnings about the virtio-iommu node, Peter Maydell, 2022/10/25
- [PULL 06/30] target/imx: reload cmp timer outside of the reload ptimer transaction, Peter Maydell, 2022/10/25
- [PULL 09/30] target/arm: Add isar predicates for FEAT_HAFDBS, Peter Maydell, 2022/10/25
- [PULL 08/30] target/arm: Add ptw_idx to S1Translate, Peter Maydell, 2022/10/25
- [PULL 04/30] hw/core/resettable: fix reset level counting, Peter Maydell, 2022/10/25
- [PULL 03/30] target/arm: honor HCR_E2H and HCR_TGE in arm_excp_unmasked(), Peter Maydell, 2022/10/25
- [PULL 10/30] target/arm: Extract HA and HD in aa64_va_parameters, Peter Maydell, 2022/10/25
- [PULL 11/30] target/arm: Move S1_ptw_translate outside arm_ld[lq]_ptw, Peter Maydell, 2022/10/25
- [PULL 15/30] target/arm: Don't shift attrs in get_phys_addr_lpae,
Peter Maydell <=
- [PULL 16/30] target/arm: Consider GP an attribute in get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 14/30] target/arm: Fix fault reporting in get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 17/30] target/arm: Tidy merging of attributes from descriptor and table, Peter Maydell, 2022/10/25
- [PULL 12/30] target/arm: Add ARMFault_UnsuppAtomicUpdate, Peter Maydell, 2022/10/25
- [PULL 13/30] target/arm: Remove loop from get_phys_addr_lpae, Peter Maydell, 2022/10/25
- [PULL 18/30] target/arm: Implement FEAT_HAFDBS, access flag portion, Peter Maydell, 2022/10/25
- [PULL 19/30] target/arm: Implement FEAT_HAFDBS, dirty bit portion, Peter Maydell, 2022/10/25
- [PULL 07/30] target/arm: Introduce regime_is_stage2, Peter Maydell, 2022/10/25
- [PULL 21/30] reset: allow registering handlers that aren't called by snapshot loading, Peter Maydell, 2022/10/25
- [PULL 23/30] x86: do not re-randomize RNG seed on snapshot load, Peter Maydell, 2022/10/25