Re: [PATCH v3] xio3130_upstream: Add ACS (Access Control Services) capability

[Paul Schlacter]

The upstream and downstream of the physical machine also have acs capability.
The virtual machine should at least have a way to see the acs

On Sun, Jan 1, 2023 at 5:03 PM Paul Schlacter <wlfightup@gmail.com> wrote:
>
> Please help review and merge the code into the master.  Thank you very much.
>
> ping
>
> On Sat, Aug 20, 2022 at 7:31 AM Paul Schlacter <wlfightup@gmail.com> wrote:
> >
> > ping
> >
> > On Thu, Aug 18, 2022 at 10:25 PM Paul Schlacter <wlfightup@gmail.com> wrote:
> > >
> > > If it is a pcie device, check that all devices on the path from
> > > the device to the root complex have ACS enabled, and then the
> > > device will become an iommu_group.
> > >
> > > pci_acs_path_enabled, this function in the Linux kernel, it means
> > > that if the device is a PCIe device, check the path from the
> > > device to the root complex. If ACS is all enabled, the device will
> > > become an iommu_group.
> > >
> > > acs determine whether it is a separate iommu_group.
> > >
> > > Signed-off-by: wlfightup <wlfightup@gmail.com>
> > > —
> > > v3:
> > > - Suggested by Michael S. Tsirkin, use x-disable-acs, and set the
> > > default value to true, Compatible with previous defaults
> > >
> > > v2:
> > > - Allow ACS to be disabled.
> > > - Suggested by Michael S. Tsirkin, use disable-acs to set property.
> > >
> > > hw/pci-bridge/xio3130_upstream.c | 13 +++++++++++++
> > > 1 file changed, 13 insertions(+)
> > >
> > > diff --git a/hw/pci-bridge/xio3130_upstream.c 
> > > b/hw/pci-bridge/xio3130_upstream.c
> > > index 5ff46ef050..f918113d76 100644
> > > --- a/hw/pci-bridge/xio3130_upstream.c
> > > +++ b/hw/pci-bridge/xio3130_upstream.c
> > > @@ -24,6 +24,7 @@
> > > #include "hw/pci/msi.h"
> > > #include "hw/pci/pcie.h"
> > > #include "hw/pci/pcie_port.h"
> > > +#include "hw/qdev-properties.h"
> > > #include "migration/vmstate.h"
> > > #include "qemu/module.h"
> > >
> > > @@ -37,6 +38,8 @@
> > > #define XIO3130_SSVID_SSID              0
> > > #define XIO3130_EXP_OFFSET              0x90
> > > #define XIO3130_AER_OFFSET              0x100
> > > +#define XIO3130_ACS_OFFSET \
> > > +        (XIO3130_AER_OFFSET + PCI_ERR_SIZEOF)
> > >
> > > static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
> > >                                         uint32_t val, int len)
> > > @@ -57,6 +60,7 @@ static void xio3130_upstream_reset(DeviceState *qdev)
> > > static void xio3130_upstream_realize(PCIDevice *d, Error **errp)
> > > {
> > >   PCIEPort *p = PCIE_PORT(d);
> > > +    PCIESlot *s = PCIE_SLOT(d);
> > >   int rc;
> > >
> > >   pci_bridge_initfn(d, TYPE_PCIE_BUS);
> > > @@ -92,6 +96,9 @@ static void xio3130_upstream_realize(PCIDevice *d, 
> > > Error **errp)
> > >       goto err;
> > >   }
> > >
> > > +    if (!s->disable_acs) {
> > > +        pcie_acs_init(d, XIO3130_ACS_OFFSET);
> > > +    }
> > >   return;
> > >
> > > err:
> > > @@ -110,6 +117,11 @@ static void xio3130_upstream_exitfn(PCIDevice *d)
> > >   pci_bridge_exitfn(d);
> > > }
> > >
> > > +static Property xio3130_upstream_props[] = {
> > > +    DEFINE_PROP_BOOL("x-disable-acs", PCIESlot, disable_acs, true),
> > > +    DEFINE_PROP_END_OF_LIST()
> > > +};
> > > +
> > > static const VMStateDescription vmstate_xio3130_upstream = {
> > >   .name = "xio3130-express-upstream-port",
> > >   .priority = MIG_PRI_PCI_BUS,
> > > @@ -139,6 +151,7 @@ static void xio3130_upstream_class_init(ObjectClass 
> > > *klass, void *data)
> > >   dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
> > >   dc->reset = xio3130_upstream_reset;
> > >   dc->vmsd = &vmstate_xio3130_upstream;
> > > +    device_class_set_props(dc, xio3130_upstream_props);
> > > }
> > >
> > > static const TypeInfo xio3130_upstream_info = {
> > > --
> > > 2.24.3 (Apple Git-128)
> > >
> > >