[RFC PATCH 37/40] target/arm: Move "cfgend" to class property

[Richard Henderson]

Remove the cfgend variable entirely and reuse the property
accessor functions created for reset-hivecs.  This removes
the last setting of cpu->reset_sctlr, to we can remove that
as well, using only the class value.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/cpu.h    |  8 --------
 target/arm/cpu.c    | 26 ++++++++++++--------------
 target/arm/helper.c |  4 ++--
 3 files changed, 14 insertions(+), 24 deletions(-)

diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5921660d86..23070a9c25 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -954,7 +954,6 @@ struct ArchCPU {
     uint32_t revidr;
     uint32_t reset_fpsid;
     uint64_t ctr;
-    uint32_t reset_sctlr;
     uint64_t pmceid0;
     uint64_t pmceid1;
     uint32_t id_afr0;
@@ -987,13 +986,6 @@ struct ArchCPU {
     int gic_vprebits; /* number of virtual preemption bits */
     int gic_pribits; /* number of physical priority bits */
 
-    /* Whether the cfgend input is high (i.e. this CPU should reset into
-     * big-endian mode).  This setting isn't used directly: instead it modifies
-     * the reset_sctlr value to have SCTLR_B or SCTLR_EE set, depending on the
-     * architecture version.
-     */
-    bool cfgend;
-
     QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks;
     QLIST_HEAD(, ARMELChangeHook) el_change_hooks;
 
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 3262e86e61..17d08e0e9c 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1222,7 +1222,6 @@ static void arm_cpu_initfn(Object *obj)
     cpu->revidr = acc->revidr;
     cpu->id_afr0 = acc->id_afr0;
     cpu->reset_fpsid = acc->reset_fpsid;
-    cpu->reset_sctlr = acc->reset_sctlr;
     cpu->reset_auxcr = acc->reset_auxcr;
     cpu->pmsav7_dregion = acc->pmsav7_dregion;
     cpu->sau_sregion = acc->sau_sregion;
@@ -1280,9 +1279,6 @@ static void arm_cpu_initfn(Object *obj)
 static Property arm_cpu_reset_cbar_property =
             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 
-static Property arm_cpu_cfgend_property =
-            DEFINE_PROP_BOOL("cfgend", ARMCPU, cfgend, false);
-
 static Property arm_cpu_has_vfp_property =
             DEFINE_PROP_BOOL("vfp", ARMCPU, has_vfp, true);
 
@@ -1442,8 +1438,6 @@ static void arm_cpu_post_init(Object *obj)
                                    &cpu->psci_conduit,
                                    OBJ_PROP_FLAG_READWRITE);
 
-    qdev_property_add_static(DEVICE(obj), &arm_cpu_cfgend_property);
-
     if (kvm_enabled()) {
         kvm_arm_add_vcpu_properties(obj);
     }
@@ -1771,14 +1765,6 @@ static void arm_cpu_realizefn(DeviceState *dev, Error 
**errp)
         return;
     }
 
-    if (cpu->cfgend) {
-        if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
-            cpu->reset_sctlr |= SCTLR_EE;
-        } else {
-            cpu->reset_sctlr |= SCTLR_B;
-        }
-    }
-
     if (!cpu->has_pmu) {
         unset_feature(env, ARM_FEATURE_PMU);
     }
@@ -2306,6 +2292,18 @@ static void arm_cpu_leaf_class_init(ObjectClass *oc, 
void *data)
     }
 
 #ifndef CONFIG_USER_ONLY
+    /*
+     * When the cfgend input is high, the CPU should reset into
+     * big-endian mode.  Modify the reset_sctlr value to have SCTLR_B
+     * or SCTLR_EE set, depending on the architecture version.
+     */
+    class_property_add(oc, "cfgend", "bool", NULL,
+                       arm_class_prop_get_sctlrbit,
+                       arm_class_prop_set_sctlrbit,
+                       (void *)(uintptr_t)
+                       (arm_class_feature(acc, ARM_FEATURE_V7)
+                        ? SCTLR_EE : SCTLR_B));
+
     if (arm_class_feature(acc, ARM_FEATURE_GENERIC_TIMER)) {
         class_property_add(oc, "cntfrq", "uint64", NULL,
                            arm_class_prop_uint64_ofs,
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 67d32c2e59..e414fa11dd 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7995,7 +7995,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
               .access = PL3_RW,
               .raw_writefn = raw_write, .writefn = sctlr_write,
               .fieldoffset = offsetof(CPUARMState, cp15.sctlr_el[3]),
-              .resetvalue = cpu->reset_sctlr },
+              .resetvalue = acc->reset_sctlr },
         };
 
         define_arm_cp_regs(cpu, el3_regs);
@@ -8331,7 +8331,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
             .access = PL1_RW, .accessfn = access_tvm_trvm,
             .bank_fieldoffsets = { offsetof(CPUARMState, cp15.sctlr_s),
                                    offsetof(CPUARMState, cp15.sctlr_ns) },
-            .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
+            .writefn = sctlr_write, .resetvalue = acc->reset_sctlr,
             .raw_writefn = raw_write,
         };
         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
-- 
2.34.1