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[PULL 08/34] target/arm: Add ARM Cortex-R52 CPU
From: |
Peter Maydell |
Subject: |
[PULL 08/34] target/arm: Add ARM Cortex-R52 CPU |
Date: |
Thu, 5 Jan 2023 16:43:51 +0000 |
From: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3
Signed-off-by: Tobias Röhmel <tobias.roehmel@rwth-aachen.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20221206102504.165775-8-tobias.roehmel@rwth-aachen.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu_tcg.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 568cbcfc524..ccde5080eb7 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -854,6 +854,47 @@ static void cortex_r5_initfn(Object *obj)
define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
}
+static void cortex_r52_initfn(Object *obj)
+{
+ ARMCPU *cpu = ARM_CPU(obj);
+
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_PMSA);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ cpu->midr = 0x411fd133; /* r1p3 */
+ cpu->revidr = 0x00000000;
+ cpu->reset_fpsid = 0x41034023;
+ cpu->isar.mvfr0 = 0x10110222;
+ cpu->isar.mvfr1 = 0x12111111;
+ cpu->isar.mvfr2 = 0x00000043;
+ cpu->ctr = 0x8144c004;
+ cpu->reset_sctlr = 0x30c50838;
+ cpu->isar.id_pfr0 = 0x00000131;
+ cpu->isar.id_pfr1 = 0x10111001;
+ cpu->isar.id_dfr0 = 0x03010006;
+ cpu->id_afr0 = 0x00000000;
+ cpu->isar.id_mmfr0 = 0x00211040;
+ cpu->isar.id_mmfr1 = 0x40000000;
+ cpu->isar.id_mmfr2 = 0x01200000;
+ cpu->isar.id_mmfr3 = 0xf0102211;
+ cpu->isar.id_mmfr4 = 0x00000010;
+ cpu->isar.id_isar0 = 0x02101110;
+ cpu->isar.id_isar1 = 0x13112111;
+ cpu->isar.id_isar2 = 0x21232142;
+ cpu->isar.id_isar3 = 0x01112131;
+ cpu->isar.id_isar4 = 0x00010142;
+ cpu->isar.id_isar5 = 0x00010001;
+ cpu->isar.dbgdidr = 0x77168000;
+ cpu->clidr = (1 << 27) | (1 << 24) | 0x3;
+ cpu->ccsidr[0] = 0x700fe01a; /* 32KB L1 dcache */
+ cpu->ccsidr[1] = 0x201fe00a; /* 32KB L1 icache */
+
+ cpu->pmsav7_dregion = 16;
+ cpu->pmsav8r_hdregion = 16;
+}
+
static void cortex_r5f_initfn(Object *obj)
{
ARMCPU *cpu = ARM_CPU(obj);
@@ -1163,6 +1204,7 @@ static const ARMCPUInfo arm_tcg_cpus[] = {
.class_init = arm_v7m_class_init },
{ .name = "cortex-r5", .initfn = cortex_r5_initfn },
{ .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
+ { .name = "cortex-r52", .initfn = cortex_r52_initfn },
{ .name = "ti925t", .initfn = ti925t_initfn },
{ .name = "sa1100", .initfn = sa1100_initfn },
{ .name = "sa1110", .initfn = sa1110_initfn },
--
2.25.1
- [PULL 00/34] target-arm queue, Peter Maydell, 2023/01/05
- [PULL 02/34] target/arm: Don't add all MIDR aliases for cores that implement PMSA, Peter Maydell, 2023/01/05
- [PULL 01/34] target/arm:Set lg_page_size to 0 if either S1 or S2 asks for it, Peter Maydell, 2023/01/05
- [PULL 03/34] target/arm: Make RVBAR available for all ARMv8 CPUs, Peter Maydell, 2023/01/05
- [PULL 04/34] target/arm: Make stage_2_format for cache attributes optional, Peter Maydell, 2023/01/05
- [PULL 05/34] target/arm: Enable TTBCR_EAE for ARMv8-R AArch32, Peter Maydell, 2023/01/05
- [PULL 08/34] target/arm: Add ARM Cortex-R52 CPU,
Peter Maydell <=
- [PULL 07/34] target/arm: Add PMSAv8r functionality, Peter Maydell, 2023/01/05
- [PULL 12/34] hw/timer/imx_epit: define SR_OCIF, Peter Maydell, 2023/01/05
- [PULL 10/34] hw/timer/imx_epit: improve comments, Peter Maydell, 2023/01/05
- [PULL 13/34] hw/timer/imx_epit: update interrupt state on CR write access, Peter Maydell, 2023/01/05
- [PULL 09/34] target/arm: fix handling of HLT semihosting in system mode, Peter Maydell, 2023/01/05
- [PULL 06/34] target/arm: Add PMSAv8r registers, Peter Maydell, 2023/01/05
- [PULL 16/34] hw/timer/imx_epit: remove explicit fields cnt and freq, Peter Maydell, 2023/01/05
- [PULL 17/34] hw/timer/imx_epit: fix compare timer handling, Peter Maydell, 2023/01/05
- [PULL 14/34] hw/timer/imx_epit: hard reset initializes CR with 0, Peter Maydell, 2023/01/05
- [PULL 19/34] target/arm: Fix checkpatch space errors in helper.c, Peter Maydell, 2023/01/05