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[PULL v3 03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2
From: |
Alistair Francis |
Subject: |
[PULL v3 03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2 |
Date: |
Fri, 6 Jan 2023 13:13:17 +1000 |
From: Richard Henderson <richard.henderson@linaro.org>
There was a typo using opc_addi instead of opc_add with the
two registers. While we're at it, simplify the gating test
to al == bl to improve dynamic scheduling even when the
output register does not overlap the inputs.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221020233836.2341671-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
tcg/riscv/tcg-target.c.inc | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 191197853f..2a84c57bec 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -700,9 +700,15 @@ static void tcg_out_addsub2(TCGContext *s,
if (cbl) {
tcg_out_opc_imm(s, opc_addi, rl, al, bl);
tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl);
- } else if (rl == al && rl == bl) {
+ } else if (al == bl) {
+ /*
+ * If the input regs overlap, this is a simple doubling
+ * and carry-out is the input msb. This special case is
+ * required when the output reg overlaps the input,
+ * but we might as well use it always.
+ */
tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0);
- tcg_out_opc_reg(s, opc_addi, rl, al, bl);
+ tcg_out_opc_reg(s, opc_add, rl, al, al);
} else {
tcg_out_opc_reg(s, opc_add, rl, al, bl);
tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0,
--
2.39.0
- [PULL v3 00/43] riscv-to-apply queue, Alistair Francis, 2023/01/05
- [PULL v3 02/43] tcg/riscv: Fix range matched by TCG_CT_CONST_M12, Alistair Francis, 2023/01/05
- [PULL v3 03/43] tcg/riscv: Fix reg overlap case in tcg_out_addsub2,
Alistair Francis <=
- [PULL v3 01/43] target/riscv: Fix PMP propagation for tlb, Alistair Francis, 2023/01/05
- [PULL v3 04/43] tcg/riscv: Fix base register for user-only qemu_ld/st, Alistair Francis, 2023/01/05
- [PULL v3 05/43] hw/riscv/opentitan: bump opentitan, Alistair Francis, 2023/01/05
- [PULL v3 06/43] hw/riscv/opentitan: add aon_timer base unimpl, Alistair Francis, 2023/01/05
- [PULL v3 07/43] target/riscv: Add smstateen support, Alistair Francis, 2023/01/05
- [PULL v3 09/43] target/riscv: generate virtual instruction exception, Alistair Francis, 2023/01/05
- [PULL v3 10/43] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2023/01/05
- [PULL v3 08/43] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2023/01/05
- [PULL v3 11/43] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2023/01/05
- [PULL v3 12/43] target/riscv: Enable native debug itrigger, Alistair Francis, 2023/01/05