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[PULL v3 15/43] target/riscv: Typo fix in sstc() predicate
From: |
Alistair Francis |
Subject: |
[PULL v3 15/43] target/riscv: Typo fix in sstc() predicate |
Date: |
Fri, 6 Jan 2023 13:13:29 +1000 |
From: Anup Patel <apatel@ventanamicro.com>
We should use "&&" instead of "&" when checking hcounteren.TM and
henvcfg.STCE bits.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221108125703.1463577-2-apatel@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 71236f2b5d..0db2c233e5 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -940,7 +940,7 @@ static RISCVException sstc(CPURISCVState *env, int csrno)
}
if (riscv_cpu_virt_enabled(env)) {
- if (!(get_field(env->hcounteren, COUNTEREN_TM) &
+ if (!(get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->henvcfg, HENVCFG_STCE))) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
--
2.39.0
- [PULL v3 05/43] hw/riscv/opentitan: bump opentitan, (continued)
- [PULL v3 05/43] hw/riscv/opentitan: bump opentitan, Alistair Francis, 2023/01/05
- [PULL v3 06/43] hw/riscv/opentitan: add aon_timer base unimpl, Alistair Francis, 2023/01/05
- [PULL v3 07/43] target/riscv: Add smstateen support, Alistair Francis, 2023/01/05
- [PULL v3 09/43] target/riscv: generate virtual instruction exception, Alistair Francis, 2023/01/05
- [PULL v3 10/43] target/riscv: Add itrigger support when icount is not enabled, Alistair Francis, 2023/01/05
- [PULL v3 08/43] target/riscv: smstateen check for h/s/envcfg, Alistair Francis, 2023/01/05
- [PULL v3 11/43] target/riscv: Add itrigger support when icount is enabled, Alistair Francis, 2023/01/05
- [PULL v3 12/43] target/riscv: Enable native debug itrigger, Alistair Francis, 2023/01/05
- [PULL v3 13/43] target/riscv: Add itrigger_enabled field to CPURISCVState, Alistair Francis, 2023/01/05
- [PULL v3 14/43] hw/intc: sifive_plic: Renumber the S irqs for numa support, Alistair Francis, 2023/01/05
- [PULL v3 15/43] target/riscv: Typo fix in sstc() predicate,
Alistair Francis <=
- [PULL v3 16/43] hw/riscv: virt: Remove the redundant ipi-id property, Alistair Francis, 2023/01/05
- [PULL v3 18/43] target/riscv: Add some comments for sstatus CSR in riscv_cpu_dump_state(), Alistair Francis, 2023/01/05
- [PULL v3 17/43] target/riscv: support cache-related PMU events in virtual mode, Alistair Francis, 2023/01/05
- [PULL v3 22/43] hw/intc: sifive_plic: fix out-of-bound access of source_priority array, Alistair Francis, 2023/01/05
- [PULL v3 19/43] hw/misc: pfsoc: add fabric clocks to ioscb, Alistair Francis, 2023/01/05
- [PULL v3 21/43] hw/{misc, riscv}: pfsoc: add system controller as unimplemented, Alistair Francis, 2023/01/05
- [PULL v3 20/43] hw/riscv: pfsoc: add missing FICs as unimplemented, Alistair Francis, 2023/01/05
- [PULL v3 23/43] target/riscv: Fix mret exception cause when no pmp rule is configured, Alistair Francis, 2023/01/05
- [PULL v3 24/43] target/riscv: Set pc_succ_insn for !rvc illegal insn, Alistair Francis, 2023/01/05
- [PULL v3 25/43] target/riscv: Simplify helper_sret() a little bit, Alistair Francis, 2023/01/05