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[PULL 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz
From: |
Richard Henderson |
Subject: |
[PULL 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz |
Date: |
Fri, 6 Jan 2023 23:51:14 -0800 |
Reuse code from movcond to conditionally copy a2 to dest,
based on the condition codes produced by FLOGR.
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target-con-set.h | 1 +
tcg/s390x/tcg-target.c.inc | 20 +++++++++++---------
2 files changed, 12 insertions(+), 9 deletions(-)
diff --git a/tcg/s390x/tcg-target-con-set.h b/tcg/s390x/tcg-target-con-set.h
index 8cf8ed4dff..baf3bc9037 100644
--- a/tcg/s390x/tcg-target-con-set.h
+++ b/tcg/s390x/tcg-target-con-set.h
@@ -24,6 +24,7 @@ C_O1_I2(r, 0, rI)
C_O1_I2(r, 0, rJ)
C_O1_I2(r, r, r)
C_O1_I2(r, r, ri)
+C_O1_I2(r, r, rI)
C_O1_I2(r, r, rJ)
C_O1_I2(r, r, rK)
C_O1_I2(r, r, rKR)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index ab1fb45cc2..8254f9f650 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -1424,15 +1424,15 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg
a1,
if (a2const && a2 == 64) {
tcg_out_mov(s, TCG_TYPE_I64, dest, TCG_REG_R0);
- } else {
- if (a2const) {
- tcg_out_movi(s, TCG_TYPE_I64, dest, a2);
- } else {
- tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
- }
- /* Emit: if (one bit found) dest = r0. */
- tcg_out_insn(s, RRFc, LOCGR, dest, TCG_REG_R0, 2);
+ return;
}
+
+ /*
+ * Conditions from FLOGR are:
+ * 2 -> one bit found
+ * 8 -> no one bit found
+ */
+ tgen_movcond_int(s, TCG_TYPE_I64, dest, a2, a2const, TCG_REG_R0, 8, 2);
}
static void tgen_deposit(TCGContext *s, TCGReg dest, TCGReg src,
@@ -3070,11 +3070,13 @@ static TCGConstraintSetIndex
tcg_target_op_def(TCGOpcode op)
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
- case INDEX_op_clz_i64:
case INDEX_op_setcond_i32:
case INDEX_op_setcond_i64:
return C_O1_I2(r, r, ri);
+ case INDEX_op_clz_i64:
+ return C_O1_I2(r, r, rI);
+
case INDEX_op_sub_i32:
case INDEX_op_sub_i64:
case INDEX_op_and_i32:
--
2.34.1
- [PULL 16/27] tcg/s390x: Issue XILF directly for xor_i32, (continued)
- [PULL 16/27] tcg/s390x: Issue XILF directly for xor_i32, Richard Henderson, 2023/01/07
- [PULL 09/27] tcg/s390x: Remove FAST_BCR_SER facility check, Richard Henderson, 2023/01/07
- [PULL 04/27] tcg/s390x: Remove USE_LONG_BRANCHES, Richard Henderson, 2023/01/07
- [PULL 07/27] tcg/s390x: Check for general-instruction-extension facility at startup, Richard Henderson, 2023/01/07
- [PULL 05/27] tcg/s390x: Check for long-displacement facility at startup, Richard Henderson, 2023/01/07
- [PULL 11/27] tcg/s390x: Use LARL+AGHI for odd addresses, Richard Henderson, 2023/01/07
- [PULL 10/27] tcg/s390x: Remove DISTINCT_OPERANDS facility check, Richard Henderson, 2023/01/07
- [PULL 13/27] tcg/s390x: Distinguish RIE formats, Richard Henderson, 2023/01/07
- [PULL 14/27] tcg/s390x: Support MIE2 multiply single instructions, Richard Henderson, 2023/01/07
- [PULL 19/27] tcg/s390x: Support MIE3 logical operations, Richard Henderson, 2023/01/07
- [PULL 23/27] tcg/s390x: Use tgen_movcond_int in tgen_clz,
Richard Henderson <=
- [PULL 25/27] tcg/s390x: Tighten constraints for 64-bit compare, Richard Henderson, 2023/01/07
- [PULL 17/27] tcg/s390x: Tighten constraints for or_i64 and xor_i64, Richard Henderson, 2023/01/07
- [PULL 18/27] tcg/s390x: Tighten constraints for and_i64, Richard Henderson, 2023/01/07
- [PULL 21/27] tcg/s390x: Generalize movcond implementation, Richard Henderson, 2023/01/07
- [PULL 26/27] tcg/s390x: Cleanup tcg_out_movi, Richard Henderson, 2023/01/07
- [PULL 24/27] tcg/s390x: Implement ctpop operation, Richard Henderson, 2023/01/07
- [PULL 20/27] tcg/s390x: Create tgen_cmp2 to simplify movcond, Richard Henderson, 2023/01/07
- [PULL 22/27] tcg/s390x: Support SELGR instruction in movcond, Richard Henderson, 2023/01/07
- [PULL 27/27] tcg/s390x: Avoid the constant pool in tcg_out_movi, Richard Henderson, 2023/01/07
- Re: [PULL 00/27] tcg/s390x patch queue, Peter Maydell, 2023/01/08