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[PATCH 22/25] hw/arm/aspeed_ast10x0: Map the secure SRAM
From: |
Cédric Le Goater |
Subject: |
[PATCH 22/25] hw/arm/aspeed_ast10x0: Map the secure SRAM |
Date: |
Thu, 19 Jan 2023 13:34:46 +0100 |
From: Philippe Mathieu-Daudé <philmd@linaro.org>
Some SRAM appears to be used by the Secure Boot unit and
crypto accelerators. Name it 'secure sram'.
Note, the SRAM base address was already present but unused
(the 'SBC' index is used for the MMIO peripheral).
Interestingly using CFLAGS=-Winitializer-overrides reports:
../hw/arm/aspeed_ast10x0.c:32:30: warning: initializer overrides prior
initialization of this subobject [-Winitializer-overrides]
[ASPEED_DEV_SBC] = 0x7E6F2000,
^~~~~~~~~~
../hw/arm/aspeed_ast10x0.c:24:30: note: previous initialization is here
[ASPEED_DEV_SBC] = 0x79000000,
^~~~~~~~~~
This fixes with Zephyr:
uart:~$ rsa test
rsa test vector[0]:
[00:00:26.156,000] <err> os: ***** BUS FAULT *****
[00:00:26.157,000] <err> os: Precise data bus error
[00:00:26.157,000] <err> os: BFAR Address: 0x79000000
[00:00:26.158,000] <err> os: r0/a1: 0x79000000 r1/a2: 0x00000000 r2/a3:
0x00001800
[00:00:26.158,000] <err> os: r3/a4: 0x79001800 r12/ip: 0x00000800 r14/lr:
0x0001098d
[00:00:26.158,000] <err> os: xpsr: 0x81000000
[00:00:26.158,000] <err> os: Faulting instruction address (r15/pc): 0x0001e1bc
[00:00:26.158,000] <err> os: >>> ZEPHYR FATAL ERROR 0: CPU exception on CPU 0
[00:00:26.158,000] <err> os: Current thread: 0x38248 (shell_uart)
[00:00:26.165,000] <err> os: Halting system
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Peter Delevoryas <peter@pjd.dev>
[ clg: Fixed size of Secure Boot Controller Memory ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
include/hw/arm/aspeed_soc.h | 3 +++
hw/arm/aspeed_ast10x0.c | 11 ++++++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h
index 9a5e3c0bac..bd1e03e78a 100644
--- a/include/hw/arm/aspeed_soc.h
+++ b/include/hw/arm/aspeed_soc.h
@@ -71,6 +71,7 @@ struct AspeedSoCState {
AspeedSMCState spi[ASPEED_SPIS_NUM];
EHCISysBusState ehci[ASPEED_EHCIS_NUM];
AspeedSBCState sbc;
+ MemoryRegion secsram;
UnimplementedDeviceState sbc_unimplemented;
AspeedSDMCState sdmc;
AspeedWDTState wdt[ASPEED_WDTS_NUM];
@@ -105,6 +106,7 @@ struct AspeedSoCClass {
const char *cpu_type;
uint32_t silicon_rev;
uint64_t sram_size;
+ uint64_t secsram_size;
int spis_num;
int ehcis_num;
int wdts_num;
@@ -143,6 +145,7 @@ enum {
ASPEED_DEV_SCU,
ASPEED_DEV_ADC,
ASPEED_DEV_SBC,
+ ASPEED_DEV_SECSRAM,
ASPEED_DEV_EMMC_BC,
ASPEED_DEV_VIDEO,
ASPEED_DEV_SRAM,
diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c
index 1a06269cb1..592a19d988 100644
--- a/hw/arm/aspeed_ast10x0.c
+++ b/hw/arm/aspeed_ast10x0.c
@@ -21,7 +21,7 @@
static const hwaddr aspeed_soc_ast1030_memmap[] = {
[ASPEED_DEV_SRAM] = 0x00000000,
- [ASPEED_DEV_SBC] = 0x79000000,
+ [ASPEED_DEV_SECSRAM] = 0x79000000,
[ASPEED_DEV_IOMEM] = 0x7E600000,
[ASPEED_DEV_PWM] = 0x7E610000,
[ASPEED_DEV_FMC] = 0x7E620000,
@@ -221,6 +221,14 @@ static void aspeed_soc_ast1030_realize(DeviceState
*dev_soc, Error **errp)
memory_region_add_subregion(s->memory,
sc->memmap[ASPEED_DEV_SRAM],
&s->sram);
+ memory_region_init_ram(&s->secsram, OBJECT(s), "sec.sram",
+ sc->secsram_size, &err);
+ if (err != NULL) {
+ error_propagate(errp, err);
+ return;
+ }
+ memory_region_add_subregion(s->memory, sc->memmap[ASPEED_DEV_SECSRAM],
+ &s->secsram);
/* SCU */
if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
@@ -400,6 +408,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass
*klass, void *data)
sc->cpu_type = ARM_CPU_TYPE_NAME("cortex-m4");
sc->silicon_rev = AST1030_A1_SILICON_REV;
sc->sram_size = 0xc0000;
+ sc->secsram_size = 0x40000; /* 256 * KiB */
sc->spis_num = 2;
sc->ehcis_num = 0;
sc->wdts_num = 4;
--
2.39.0
- [PATCH 14/25] hw/nvram/eeprom_at24c: Make reset behavior more like hardware, (continued)
- [PATCH 14/25] hw/nvram/eeprom_at24c: Make reset behavior more like hardware, Cédric Le Goater, 2023/01/19
- [PATCH 15/25] target/arm: Allow users to set the number of VFP registers, Cédric Le Goater, 2023/01/19
- [PATCH 17/25] hw/watchdog/wdt_aspeed: Extend MMIO range to cover more registers, Cédric Le Goater, 2023/01/19
- [PATCH 18/25] hw/watchdog/wdt_aspeed: Log unimplemented registers as UNIMP level, Cédric Le Goater, 2023/01/19
- [PATCH 20/25] hw/arm/aspeed_ast10x0: Add various unimplemented peripherals, Cédric Le Goater, 2023/01/19
- [PATCH 21/25] hw/arm/aspeed_ast10x0: Map I3C peripheral, Cédric Le Goater, 2023/01/19
- [PATCH 16/25] hw/watchdog/wdt_aspeed: Rename MMIO region size as 'iosize', Cédric Le Goater, 2023/01/19
- [PATCH 24/25] hw/arm/aspeed_ast10x0: Add TODO comment to use Cortex-M4F, Cédric Le Goater, 2023/01/19
- [PATCH 19/25] hw/misc/aspeed_hace: Do not crash if address_space_map() failed, Cédric Le Goater, 2023/01/19
- [PATCH 22/25] hw/arm/aspeed_ast10x0: Map the secure SRAM,
Cédric Le Goater <=
- [PATCH 23/25] hw/arm/aspeed_ast10x0: Map HACE peripheral, Cédric Le Goater, 2023/01/19
- [PATCH 25/25] tests/avocado: Test Aspeed Zephyr SDK v00.01.08 on AST1030 board, Cédric Le Goater, 2023/01/19