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[PATCH 15/22] target/arm: Use get_phys_addr_with_struct in S1_ptw_transl
From: |
Richard Henderson |
Subject: |
[PATCH 15/22] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate |
Date: |
Mon, 23 Jan 2023 14:00:20 -1000 |
Do not provide a fast-path for physical addresses,
as those will need to be validated for GPC.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 35 ++++++++++++++---------------------
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 6b6f8195eb..37f5ff220c 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -234,29 +234,22 @@ static bool S1_ptw_translate(CPUARMState *env,
S1Translate *ptw,
* From gdbstub, do not use softmmu so that we don't modify the
* state of the cpu at all, including softmmu tlb contents.
*/
- if (regime_is_stage2(s2_mmu_idx)) {
- S1Translate s2ptw = {
- .in_mmu_idx = s2_mmu_idx,
- .in_ptw_idx = arm_space_to_phys(space),
- .in_space = space,
- .in_secure = is_secure,
- .in_debug = true,
- };
- GetPhysAddrResult s2 = { };
+ S1Translate s2ptw = {
+ .in_mmu_idx = s2_mmu_idx,
+ .in_ptw_idx = arm_space_to_phys(space),
+ .in_space = space,
+ .in_secure = is_secure,
+ .in_debug = true,
+ };
+ GetPhysAddrResult s2 = { };
- if (get_phys_addr_lpae(env, &s2ptw, addr, MMU_DATA_LOAD,
- false, &s2, fi)) {
- goto fail;
- }
- ptw->out_phys = s2.f.phys_addr;
- pte_attrs = s2.cacheattrs.attrs;
- pte_secure = s2.f.attrs.secure;
- } else {
- /* Regime is physical. */
- ptw->out_phys = addr;
- pte_attrs = 0;
- pte_secure = is_secure;
+ if (get_phys_addr_with_struct(env, &s2ptw, addr,
+ MMU_DATA_LOAD, &s2, fi)) {
+ goto fail;
}
+ ptw->out_phys = s2.f.phys_addr;
+ pte_attrs = s2.cacheattrs.attrs;
+ pte_secure = s2.f.attrs.secure;
ptw->out_host = NULL;
ptw->out_rw = false;
} else {
--
2.34.1
- [PATCH 07/22] target/arm: Introduce ARMSecuritySpace, (continued)
- [PATCH 07/22] target/arm: Introduce ARMSecuritySpace, Richard Henderson, 2023/01/23
- [PATCH 08/22] include/exec/memattrs: Add two bits of space to MemTxAttrs, Richard Henderson, 2023/01/23
- [PATCH 09/22] target/arm: Adjust the order of Phys and Stage2 ARMMMUIdx, Richard Henderson, 2023/01/23
- [PATCH 10/22] target/arm: Introduce ARMMMUIdx_Phys_{Realm,Root}, Richard Henderson, 2023/01/23
- [PATCH 12/22] target/arm: NSTable is RES0 for the RME EL3 regime, Richard Henderson, 2023/01/23
- [PATCH 11/22] target/arm: Pipe ARMSecuritySpace through ptw.c, Richard Henderson, 2023/01/23
- [PATCH 13/22] target/arm: Handle Block and Page bits for security space, Richard Henderson, 2023/01/23
- [PATCH 14/22] target/arm: Handle no-execute for Realm and Root regimes, Richard Henderson, 2023/01/23
- [PATCH 16/22] target/arm: Move s1_is_El0 into S1Translate, Richard Henderson, 2023/01/23
- [PATCH 17/22] target/arm: Use get_phys_addr_with_struct for stage2, Richard Henderson, 2023/01/23
- [PATCH 15/22] target/arm: Use get_phys_addr_with_struct in S1_ptw_translate,
Richard Henderson <=
- [PATCH 18/22] target/arm: Add GPC syndrome, Richard Henderson, 2023/01/23
- [PATCH 19/22] target/arm: Implement GPC exceptions, Richard Henderson, 2023/01/23
- [PATCH 20/22] target/arm: Implement the granule protection check, Richard Henderson, 2023/01/23
- [PATCH 21/22] target/arm: Enable RME for -cpu max, Richard Henderson, 2023/01/23
- [RFC PATCH 22/22] hw/arm/virt: Add some memory for Realm Management Monitor, Richard Henderson, 2023/01/23